• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.2
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• pp.190-193
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• 2022

In this work, the effect of sputtering working pressure for the tellurium film and its thin-film transistor was investigated. The transfer characteristics of tellurium thin-film transistors were improved by increasing the working pressure during sputtering process. As increasing working pressure, physical and optical properties of Te films such as crystallinity, transmittance, and surface roughness were improved. Therefore, the improved transfer characteristics of Te thin-film transistors may originate from both improved interface properties between the silicon oxide gate dielectric layer and the tellurium active layer with an improved quality of Te film. In conclusion, the control of working pressure during sputtering would be important for obtaining high-performance tellurium-based thin film transistor

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.6
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• pp.411-418
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• 2019

Light-triggered thyristors (LTTs) are essential components in high-power applications, such as HVDC transmission and several pulsed-power applications. Generally, LTT fabrication includes a deep diffusion of aluminum as a p-type dopant to form a uniform p-base region, which needs careful concern for contamination and additional facilities in silicon semiconductor manufacturing factories. We fabricated 4-inch 5,000 V LTTs with boron implantation and diffusion process as a p-type dopant. The LTT contains a main cathode region, edge termination designed with a variation of lateral doping, breakover diode, integrated resistor, photosensitive area, and dV/dt protection region. The doping concentration of each region was adjusted with different doses of boron ion implantation. The fabricated LTTs showed good light triggering characteristics for a light pulse of 905 nm and a blocking voltage (V_DRM) of 6,500 V. They drove an average on-state current (I_TAVM) of 2,270 A, peak nonrepetitive surge current (I_TSM) of 61 kA, critical rate of rise of on-state current (di/dt) of 1,010 A/㎲, and limiting load integral (I²T) of 17 MA²s without damage to the device.

• Progress in Medical Physics
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• v.6 no.1
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• pp.49-57
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• 1995

The semiconductor detector has a high sensitive to radiation and a small volume. It has been frequently used in high energy photon and electron beamdosimetry. However, Semiconductor detector are subject to radiation damage in high energy radiation beam which reduces the sensitivity and creat a large discrepancy. In this experiments, P-type semiconductor was irradiated to 18 MeV electron beam with pre-irradiation for reducing the sensitivity for high reproducibility and investigated the dose characteristics against the dose rate variations. The sensitivity per unit dose in small dose rate showed a 35％ large different to a large dose rate with pre-irradiation dose for 0.5 KGy and 20％ for 3 KGyin this study. The silicon detector has showed a large dependency of beam direction with 13％ discrepancy and a linear sensitive as increased temperature.

• The Journal of Korean Institute of Information Technology
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• v.16 no.11
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• pp.61-68
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• 2018

This paper describes design of a 10.525 GHz self oscillating mixer semiconductor IC chip combining voltage controlled oscillator and frequency mixer using silicon CMOS technology for Doppler radar applications. The p-core type VCO included in the self oscillating mixer minimizes the noise contained in the transmitted signal. This noise minimization increases the sensing distance and acts in a direction favorable to the reaching distance and the sensitivity of the motion detection sensor. Simulation results for phase noise show that a VCO designed as a P-core has a noise characteristic of -106.008 dBc / Hz at 1 MHz offset and -140.735 dBc / Hz at 25 MHz offset compared to a VCO designed with N-core and NP-core showed excellent noise characteristics. If a self-oscillating mixer is implemented using a p-core designed VCO in this study, a motion sensor with excellent range and reach sensitivity will be produced.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.355-358
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• 2004

In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.81-82
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• 2006

SOI(Silicon-On-Insulator) MOSFET의 전기적 특성에 미치는 게이트 산화막과 계면준위 밀도의 관계를 조사하였다. 결함이 발생하지 않는 얕은 소스/드레인 접합을 형성하기 위하여 급속열처리를 이용한 고상확산방법으로 제작한 SOI MOSFET 소자는 급속열처리 과정에서 계면준위가 증가하여 소자의 특성이 열화된다. 이를 개선하기 위하여 $H_2/N_2$ 분위기에서 후속 열처리 공정을 함으로써 소자의 특성이 향상됨을 볼 수 있었다. 이와같이 급속열처리 공정과 $H_2/H_2$ 분위기에서의 후속 열처리 공정이 소자 특성에 미치는 영향을 분석하기 위하여 소자 시뮬레이션을 이용하여 게이트 산화막과 채널 사이의 계면준위 밀도를 분석하였다. 그 결과, n-MOSFET의 경우에는 acceptor-type trap, p-MOSFET의 경우에는 donor-type trap density가 소자특성에 큰 영향을 미치는 것을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.10-15
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• 2006

Various sizes of erbium/platinum silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from $20{\mu}m$ to 10nm. The manufactured SB-MOSFETs show excellent DIBL and subthreshold swing characteristics due to the existence of Schottky barrier between source and channel. It is found that the minimization of trap density between silicide and silicon interface and the reduction of the underlap resistance are the key factors for the improvement of short channel characteristics. The manufactured 10 nm n-type SBMOSFET showed $550{\mu}A/um$ saturation current at $V_{GS}-V_T$ = $V_{DS}$ = 2V condition ($T_{ox}$ = 5nm) with excellent short channel characteristics, which is the highest current level compared with reported data.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.471-474
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• 2000

A flat type microgas sensor was fabricated on the p-type silicon wafer with low stress S $i_3$ $N_4$, whose thickness is 2${\mu}{\textrm}{m}$ using MEMS technology and its characteristics were investigated. W $O_3$thin film as a sensing material for detection of N $O_2$gas was deposited using a tungsten target by sputtering method, followed by thermal oxidation at several temperatures (40$0^{\circ}C$~$600^{\circ}C$) for one hour. N $O_2$gas sensitivities were investigated for the W $O_3$thin films with different annealing temperatures. The highest sensitivity when operating at 20$0^{\circ}C$ was obtained for the samples annealed at $600^{\circ}C$. As the results of XRD analysis, the annealed samples had polycrystalline phase mixed with triclinic and orthorhombic structures. The sample exhibit higher sensitivity when the system has less triclinic structure. The sensitivities, $R_{gas}$ $R_{air}$ operating at 20$0^{\circ}C$ to 5 ppm N $O_2$of the sample annealed at $600^{\circ}C$ were approximately 90. 90.

• Journal of Sensor Science and Technology
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• v.8 no.3
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• pp.283-290
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• 1999

The $n^+/p/p^+$ junction PERL solar cell of $0.1{\sim}2{\Omega}{\cdot}cm$ (100) p type silicon wafer was fabricated through the following steps; that is, wafer cutting, inverted pyramidally textured surfaces etching by KOH, phosphorus and boron diffusion, anti-reflection coating, grid formation and contact annealing. At this time, the optical characteristics of device surface and the efficiency of doping concentration for resistivity were investigated. And diffusion depth and doping concentration for n+ doping were simulated by silvaco program. Then their results were compared with measured results. Under the illumination of AM (air mass)1.5, $100\;mW/cm^2$ $I_{sc}$, $V_{oc}$, fill factor and the conversion efficiency were 43mA, 0.6 V, 0.62. and 16% respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.