• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.8
• /
• pp.56-62
• /
• 1992

This paper is analyzed the charge trapping and electrical properties of 0(Oxide), NO(Nitrided oxide) and ONO(Reoxidized nitrided oxide) as dielectric films in MIS structures. We have processed bottom oxide and top oxide by the thermal method, and nitride(Si$_{3}N_{4}$) by the LPCVD(Low Pressure Chemical Vapor Deposition) method on P-type(100) Silicon wafer. We have studied the charge trapping properties of the dielectrics by using a computer controlled DLTS system. All of the dielectric films are shown peak nearly at 300K. Those are bulk traps. Many trap densities which is detected in NO films, but traps. Many trap densities which is detected in NO films. Varing the nitride thickness, the trap densities of thinner nitride is decreased than the thicker nitride. Finally we have found that trap densities of ONO films is affected by nitride thickness.

• ETRI Journal
• /
• v.20 no.1
• /
• pp.37-45
• /
• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.11a
• /
• pp.115-116
• /
• 2005

Si nanowires (NWs) were fabricated in vacuum furnace by using a Nd:YAG pulsed laser with the wavelength of 325 nm. Commercial p-type Si wafer is used for target, and any catalytic materials are not used. Scanning electron microscopy (SEM) images indicate that the diameters of Si NWs ranged from 10 to 150 nm. Si NWs have various size and shape with a substrate position inside a furnace, and their morphologic construction is reproducible. The formation mechanism of the NWs is discussed.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.136-136
• /
• 2011

반도체 및 전자기기 산업에 있어서 NVM은 아주 중요한 부분을 차지하고 있다. NVM은 디스플레이 분야에 많은 기여를 하고 있는데, 측히 AMOLED에 적용이 가능하여 온도에 따라 변하는 구동 전류, 휘도, color balance에 따른 문제를 해결하는데 큰 역할을 한다. 본 연구에서는 bottom gate 구조의 nc-Si NVM 실험을 진행하였다. P-type silicon substrate (0.01~0.02 ${\Omega}-cm$) 위에 Blocking layer 층인 SiO2 (SiH4:N2O=6:30)를 12.5nm증착하였고, Charge trap layer 층인 SiNx (SiH4:NH3=6:4)를 20 nm 증착하였다. 마지막으로 Tunneling layer 층인 SiOxNy은 N2O (2.5 sccm) 플라즈마 처리를 통해 2.5 nm 증착하였다. 이러한 ONO 구조층 위에 nc-Si을 50 nm 증착후에 Source와 Drain 층을 Al 120 nm로 evaporator 이용하여 증착하였다. 제작한 샘플을 전기적 특성인 Threshold voltage, Subthreshold swing, Field effect mobility, ON/OFF current ratio, Programming & Erasing 특성, Charge retention 특성 등을 알아보았다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.1
• /
• pp.83-87
• /
• 2003

In the present paper we suggested a parallel branch structure of aluminum spiral inductor for the use of RF integrated circuit at 1∼3 GHz. The inductor was implemented on p-type silicon wafer (5∼15Ω-cm) under the standard CMOS process and it showed a enhanced qualify(Q) factor by more than 10 % with no degradation of inductance. The effect of the structure modification on the Q factor and the inductance was scrutinized comparing with conventional spital inductors

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.589-590
• /
• 2006

A novel Triple-Well P-type Triggered Silicon Controlled Rectifier (TWPTSCR) for on-chip ESD protection implemented with a triple-well CMOS technology is presented. Unlike conventional SCR devices, the proposed TWPTSCR offers a reduced triggering voltage level as well as the enhanced ESD performance of the SCR devices. From the experimental results, the TWPTSCR with a device width of 20um has the triggering voltage of 1.1V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.207-210
• /
• 1999

The objective of this study Is to deposited the preparation of SrTiO$_3$3 dielectric thin films on Ag/barrier-mater/Si(N-type 100) bottom electrode using a conventional rf-magnetron sputtering technique with a ceramic target under various conditions. It is demonstrated that the leakage current of films are strongly dependent on the atmosphere during deposition and the substrate temperature. The resistivity properties of films deposited on silicon substrates were very high resistivity. Capacitance of the films properties were the highest value(1000pF) and dependent on substrate temperature.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.4
• /
• pp.373-377
• /
• 2004

We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.10
• /
• pp.817-821
• /
• 2000

In this work, we have investigated the dependence of annealing temperature(T$\_$a/) on optical and electrical properties of amorphous hydrogenated SiC(a-SiC:H) films. The a-SiC:H films were deposited on corning glass and p-type Si(100) wafer by PECVD (plasma enhanced vapor deposition) using SiH$_4$+CH$_4$+N$_2$ gas mixture. The experimental results have shown that the optical energy band gap(E$\_$opt/)of the thin films annealed at high temperatures have shown that the graphitization of carbon clusters and micro-crystalline silicon occurs. The current-voltage characteristics have shown good electrical properties at the annealed films.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2009.05a
• /
• pp.52.1-52.1
• /
• 2009

Cupric oxide (CuO) is a p-type semiconductor with band gap of ~1.7 eV and reported to be suitable for catalysis, lithium-copper oxide electrochemical cells, and gas sensors applications. The nanoparticles, plates and nanowires of CuO were found sensing to NO2, H2S and CO. In this work, we report about the comparison about hydrogen sensing of nano thin film and nanowires structured CuO deposited on single-walled carbon nanotubes (SWNTs). The thin film and nanowires are synthesized by deposition of Cu on different substrate followed by oxidation process. Nano thin films of CuO are deposited on thermally oxidized silicon substrate, whereas nanowires are synthesized by using a porous thin film of SWNTs as substrate. The hydrogen sensing properties of synthesized materials are investigated. The results showed that nanowires cupric oxide deposited on SWNTs showed higher sensitivity to hydrogen than those of nano thin film CuO did.