• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.335-336
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• 2009

저가격 고효율 실리콘 태양전지를 구현하기 위하여 핵심적으로 적용되는 공정인 SOD(Spin on Doping) 확산공정 최적화에 관하여 연구하였다. n-type 도핑 물질로는 인(P509)을 사용하였으며, Spinning 속도와 Spinning 시간을 각 3000 rpm, 30 초로 고정하고 급속 열처리로에서 확산 온도와 확산 시간을 $800\;^{\circ}C\;{\sim}\;950\;^{\circ}C$, 2 분에서 20 분까지 가변하며 확산공정을 실시하였다. 4-Point Probe 장비로 에미터 표면 저항을 측정한 결과 확산 온도 $850\;^{\circ}C$에서 5분간 열처리 하여 확산 공정을 하였을 때 저가의 고효율 실리콘 태양전지를 구현하는데 적용 하기위한 $30\;{\sim}\;50\;{\Omega}$-sq의 에미터 표면 저항을 만족 시키는 $36\;{\Omega}$-sq의 값을 얻을 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• New & Renewable Energy
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• v.8 no.1
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• pp.24-34
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• 2012

The main issue of boron doped p-type czochralski-grown silicon solar cells is the degradation when they are exposed to light or minority carriers injection. This is due to the meta-stable defect such as boron-oxygen in the Cz-Si material. Although a clear explanation is still researching, recent investigations have revealed that the Cz-Si defect is related with the boron and the oxygen concentration. They also revealed how these defects act a recombination centers in solar cells using density function theory (DFT) calculation. This paper reviews the physical understanding and gives an overview of the degradation models. Therefore, various methods for avoiding the light-induced degradation in Cz-Si solar cells are compared in this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.58-61
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• 2012

In our report a relatively simple process for fast nano-texturing of p-type(100) CZ- silicon surface using silver catalyzed wet chemical etching in aqueous hydrofluoric acid (HF) and hydrogen peroxide solution($H_2O_2$) at room temperature. The wafers were saw-damaged by NaOH(6 wt%) at $60^{\circ}C$ for 150s. To obtain a nano-structured black surface, a thin layer of silver with thickness of 1 - 10 nm was deposited on the surfaces by evaporation system. After this process the samples were etched in HF : $H_2O_2$ : $H_2O$ = 1:5:10 at room temperature for 80s - 220s. Due to the local catalytic of the Ag clusters, this treatment results in the nano-scale texturing on the surface. This resulted in average reflectance values less than 9% after the silver on the surface of the wafers were removed.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.348-351
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• 1995

A modified silicon direct bonding method has been developed alloying an intimate contact between grooved and smooth mirror-polished oxide-free silicon wafers. A regular set of grooves was formed during preparation of heavily doped $p^+$-type grid network by oxide-masking und boron diffusion. Void-free bonded interfaces with filing of the grooves were observed by x-ray diffraction topography, infrared, optical. and scanning electron microscope techniques. The presence of regularly formed grooves in bending plane results in the substantial decrease of dislocation over large areas near the interface. Moreover two strongly misoriented waters could be successfully bonded by new technique. Diodes with bonded a pn-junction yielded a value of the ideality factor n about 1.5 and the uniform distribution of series resistance over the whole area of horded pn-structure. The suitability of the modified technique was confirmed by I - V characteristics of power diodes and reversly switched-on dynistor(RSD) with a working area about $12cm^2$. Both devices demonstrated breakdown voltages close to the calculation values.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.364.1-364.1
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• 2014

고효율 태양전지로 가기 위해서는 태양전지의 후면 패시베이션은 중요한 역할을 한다. 후면 패시베이션 막으로 사용되는 $Al_2O_3$ 막은 $Al_2O_3/Si$ 계면에서 높은 화학적 패시베이션과 Negative Fixed Charge를 가지고 있어 적합한 Barrier막으로 여겨진다. 하지만 이후에 전면 Metal paste의 소성 공정에 의해 $800^{\circ}C$이상 온도를 올려주게 됨에 따라 $Al_2O_3$ 막 내부에 결합되어 있던 수소들이 방출되어 blister가 생성되고 막 질은 떨어지게 된다. 우리는 blister가 생성되는 것을 방지하기 위한 방법으로 PECVD 장비로 SiNx를 증착하는 공정 중에 $N_2O$ 가스를 첨가하여 SiON 막을 증착하였다. SiON막은 $N_2O$가스량을 조절하여 막의 특성을 변화시키고 변화에 따라 소성시 막에 미치는 영향에 대하여 조사하였다. 공정을 위해 $156{\times}156mm2$, $200{\mu}m$, $0.5-3.0{\Omega}{\cdot}cm$ and p-type 단결정 실리콘 웨이퍼를 사용하였고, $Al_2O_3$ 막을 올리기 전에 RCA Cleaning 실행하였다. ALD 장비를 통해 $Al_2O_3$ 막을 10nm 증착하였고 RF-PECVD 장비로 SiNx막과 SiON막을 80nm 증착하였다. 소성로에서 $850^{\circ}C$ ($680^{\circ}C$) 5초동안 소성하고 QSSPC를 통해 유효 반송자 수명을 알아보았다.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.57-61
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• 2011

To develop high efficiency crystalline solar cells, the rear surface passivation is very important. In this paper, $Al_2O_3$ films deposited by thermal ALD(atomic layer deposition) method were studied for rear surface passivation of crystalline solar cells and their passivation properties were evaluated. After the deposition of $Al_2O_3$ films on p-type Si wafers, the lifetime was increased very much due to the reduction of interface state density and the field effects of the negative fixed charge in the films. Also, optimum annealing condition and effects of SiNx capping layer were investigated. The best lifetime was obtained when the films were annealed at $400^{\circ}C$ for 15min. And the lifetime degradation of the $Al_2O_3$ films with SiNx capping layers was improved compared to those without the capping layers.

• Transactions of the Korean hydrogen and new energy society
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• v.3 no.2
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• pp.17-24
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• 1992

Hydrogen gas sensors were fabricated after the form of metal/insulator/semiconductor(MIS) structure on a p-type silicon wafer and a insulating layer (silicon dioxide) thickness was changed from $500{\AA}$ to $5000{\AA}$. Their electrical properties were investigated with the variation of the hydrogen gas concentration at room temperature. At the applied forward bias of lV to both ends of Pd-MIS sensors the current was decreased logarithmically with the increase of hydrogen concentration in air. In the case of a thin $SiO_2$ layered ($500{\AA}$) sensor the current ratio was decreased to 25 % at 1 % of hydrogen concentration in air and 50% for a thick $SiO_2$ layered ($5000{\AA}$) sensor. And the response time of the thick insulating layered sensor to 1% hydrogen containing air was about 50 seconds and regeneration time was 2.5 minutes. When a 0.5mA current was appied to the thick insulating layered sensor the maximun voltage shift was calculated to 0.8V in the case of ${\theta}$ = 1 and the Pd surface coverage of hydrogen was increased logarithmically with hydrogen partial pressure.