• Transactions on Electrical and Electronic Materials
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• v.3 no.2
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• pp.10-15
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• 2002

In this paper, the electrical characteristics of fabricated p+-n junction diode are demonstrated and interpreted with different theoretical calculations. Dopants distribution by boron ion implantation on silicon wafer were simulated with TRIM-code and ICECaEM simulator. In order to make electrical activation of implanted carriers, thermal annealing treatments are carried out by RTP method for 1min. at $1000^{circ}C$ under inert $N_2$ gas condition. In this case, profiles of dopants distribution before and after heat treatments in the substrate are observed from computer simulations. In the I-V characteristics of fabricated diodes, an analytical description method of a new triangular junction model is demonstrated and the results with calculated triangular junction are compared with measured data and theoretical calculated results of abrupt junction. Forward voltage drop with new triangular junction model is lower than the case of abrupt junction model. In the C-V characteristics of diode, the calculated data are compared with the measured data. Another I-V characteristics of diodes are measured after proton implantation in electrical isolation method instead of conventional etching method. From the measured data, the turn-on characteristics after proton implantation is more improved than before proton implantation. Also the C-V characteristics of diode are compared with the measured data before proton implantation. From the results of measured data, reasonable deviations are showed. But the C-V characteristics of diode after proton implantation are deviated greatly from the calculated data because of leakage currents in defect regions and layer shift of depletion by proton implantation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.3
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• pp.33-39
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• 1983

New Schottky devices with thin stepped oxide layer (about 1000 ${\AA}$) along the edge of metal-semiconductor junction have been designed and fabricated. The breakdown voltages of these diodes have been compared with those of conventional metal overlap and P guard ring Schottky diode structures. Thin stepped oxide layer has been grown by the process of T.C.E. oxidation. In order to compare and demonstrate the improved down phenomena of these devices, conventional metal overlap diode and P guard ring which have the same dimension with new devices have also been integrated in a same New Schottty devices structured with thin stepped oxide layer have shown significant improvement in breakdown phenomena compared with conventional diodes.

• Korean Journal of Materials Research
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• v.21 no.1
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• pp.34-38
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• 2011

In this study, the effects of an annealed buffer layer with different thickness on heterojunction diodes based on the ZnO/ZnO/p-Si(111) systems were reported. The effects of an annealed buffer layer with different thickness on the structural, optical, and electrical properties of zinc oxide (ZnO) films on p-Si(111) were also studied. Before zinc oxide (ZnO) deposition, different thicknesses of ZnO buffer layer, 10 nm, 30 nm, 50 nm and 70 nm, were grown on p-Si(111) substrates using a radio-frequency sputtering system; samples were subsequently annealed at $700^{\circ}C$ for 10 minutes in $N_2$ in a horizontal thermal furnace. Zinc oxide (ZnO) films with a width of 280nm were also deposited using a radio-frequency sputtering system on the annealed ZnO/p-Si (111) substrates at room temperature; samples were subsequently annealed at $700^{\circ}C$ for 30 minutes in $N_2$. In this experiment, the structural and optical properties of ZnO thin films were studied by XRD (X-ray diffraction), and room temperature PL (photoluminescence) measurements, respectively. Current-voltage (I-V) characteristics were measured with a semiconductor parameter analyzer. The thermal tensile stress was found to decrease with increasing buffer layer thickness. Among the ZnO/ZnO/p-Si(111) diodes fabricated in this study, the sample that was formed with the condition of a 50 nm thick ZnO buffer layer showed a strong c-axis preferred orientation and I-V characteristics suitable for a heterojunction diode.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.99-105
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• 1997

The new classified model for N-p heterojunction diode is derived and used extensively in analyzing the current-voltage(I-V) characteristics of the HBTs. A new classification method is presented in order to simplify I-V equations and easily applied to the modeling of HBTs. This classification method is characterized by the properties of devices such as high level injection, the thickness of one or both bulk regions, the surface recombination and the generation-recombination. The simulation results using the proposed model agree well with the experimentally observed I-V behaviors and show good efficiencies in its application to HBTs with respect to mathematical formulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.221-221
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• 2006

The SMD type P-N junction diode with ceramic package for diode case were fabricated. It was made this diode with simple process from $Al_2O_3$ ceramic chip, solder preform, diode chip, coating reagent and conductive paste for chip terrmination. Its merit is small size, easy manufacture. fast cooling with ceramic case. The electric characteristics of the diode such as reverse recovery time, breakdown voltage, forward voltage, and leakage current were 5 28ns, 1322V, 1.08V, $0.45{\mu}A$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.974-979
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• 2009

We studied solution-processed single-layered phosphorescent organic light-emitting diodes (PHOLEDs), doped with ionic salt and treated with simultaneous electrical and thermal annealing. Because the simultaneous annealing causes the accumulation of salt ions at the electrode surfaces, the energy levels of the organic molecules are bent by the electric fields due to the adsorbed ions, i.e., the simultaneous annealing can induce the proper formation of an ionic p-i-n structure. As a result, an ionic p-i-n PHOLED with a peak luminescence of over ${\sim}35,000\;cd/m^2$ and efficiency of 27 cd/A was achieved through increased and balanced carrier-injections.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.6 no.2
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• pp.3-10
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• 1995

In this paper, the phase shifter using the p-i-n diode is designed and analyze. The large phase shift can be achieved by the swithched-line and the hybrid branch line phase shifter, however the small phase shift can be achieved by the loaded-line phase shifter, according to the bias state of the p-i-n niode. The results of the experiment agree with those of computer simulation at the center frequency.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1340-1343
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• 2007

We have simultaneously fabricated LTPS TFTs and integrated photodiodes on the same glass substrates without any additional LTPS process. The structure of an integrated photodiode is a lateral p-i-n diode with a gate. The performances of a photodiode were improved at a negative gate voltage.

• Korean Journal of Materials Research
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• v.18 no.7
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• pp.379-383
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• 2008

We report on the light-emitting diode (LED) characteristics of core-shell CdSe/ZnS nanocrystal quantum dots (QDs) embedded in $TiO_2$thin films on a Si substrate. A simple p-n junction could be formed when nanocrystal QDs on a p-type Si substrate were embedded in ${\sim}5\;nm$ thick $TiO_2$ thin film, which is inherently an n-type semiconductor. The $TiO_2$ thin film was deposited over QDs at $200^{\circ}C$ using plasma-enhanced metallorganic chemical vapor deposition. The LED structure of $TiO_2$/QDs/Si showed typical p-n diode currentvoltage and electroluminescence characteristics. The colloidal core-shell CdSe/ZnS QDs were synthesized via pyrolysis in the range of $220-280^{\circ}C$. Pyrolysis conditions were optimized through systematic studies as functions of synthesis temperature, reaction time, and surfactant amount.