• Proceedings of the Korean Vacuum Society Conference
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• 1994.02a
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• pp.109-110
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• 1994

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.63-73
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• 2004

A simple analytical model has been presented for the study of the optical bistability using a $GaAs-Al_{0.32}Ga_{0.68}As$ multiple quantum well (MQW) p-i-n diode structure. The calculation of the optical absorption is based on a semi-emperical model which is accurately valid for a range of wells between 5 and 20 nm and the electric field F< 200kV/cm . The electric field dependent analytical expression for the responsivity is presented. An attempt has been made to derive the analytical relationship between the incident optical power ( $(P_{in})$ ) and the voltage V across the device when the diode is reverse biased by a power supply in series with a load resistor. The relationship between $P_{in}$ and $P_{out}$ (i.e. transmitted optical power) is also presented. Numerical results are presented for a typical case of well size $L_Z=10.5nm,\;barrier\;size\;L_B=9.5nm$ optical wave length l = 851.7nm and electric field F? 100kV/cm. It has been shown that for the values of $P_{in}$ within certain range, the device changes its state in such a way that corresponding to every value of $P_{in}$ , two stable states and one unstable state of V as well as of $P_{out}$ are obtained which shows the optically controlled bistable nature of the device.

• Journal of the Korean Institute of Telematics and Electronics
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• v.7 no.2
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• pp.33-42
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• 1970

This report is concerned with the fahrication with the falricationof silicon VVC diode by the double diffusion planer technique. At first, some design charts for VVC diode were derived by considering the voltage-capacitance relations, the critical field intensity at the metallurgical junction, and the cut-off frequency of the diode. These charts enables the fabrication engineers to design VVC diode easily without going into the sophisticated design theory. We started with a 2.5 ohm-cm n-type epitaxial silicon wafer. The phosphorous was diffused by POCl3 impurity source. Then boron diffusion followed make hyperabrupt p-n junction by BN source. The maximum to minimum capacitance ratio of the diode as a tuning diode for a TV tuner made in these experiments was 4:1. Measured electrical characteristics of the sample diodes showed in good agreement with the theoretical expectations. Slicing and polishing technique of the silicon wafer and diffusion technique of the impurity atoms, which were employed in our study, are also stated briefly in this report.

• Korean Chemical Engineering Research
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• v.54 no.2
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• pp.274-277
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• 2016

Effects of interlayer insertion between multi-quantum well and electron blocking layer of green light emitting diode on diode performances were studied by device simulation. Dependence of Mg doping depth on characteristics of current-voltage, emitting wavelength, leakage current, and external quantum efficiency was investigated, and the optimum diode structure was presented. Device structures with interlayers doped in entire region and up to 30 nm showed remarkable reduced leakage current and effectively relieved efficiency droop which is one of the biggest challenges in green light emitting diode. Furthermore, the most improved characteristics in current-voltage and electroluminescence was obtained by the latter structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.121-121
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• 2008

We propose a novel nanomaterial-based pn diode which constructed with an n-type ZnO nanowire (NW) and a p-type HgTe nanoparticle (NP) thin film. The photo current characteristics of a ZnO NW, a HgTe NP thin film and pn diode constructed with a ZnO NW and a HgTe NP thin film were investigated under illumination of the 325 nm and 633 nm wavelength light. The conductivities of a ZnO NW exposed to the 325 nm and 633 nm wavelength light increased, while the photocurrents taken from the HgTe NP thin film was very close to the dark currents. Moreover, The pn diode exhibited the rectifying characteristics of the dark current and of the photocurrent excited by the 633 nm wavelength light. In contrast, the ohmic characteristics for the photocurrent were observed due to the junction barrier lowering in the conduction band of the ZnO nanowire under the illumination of the 325 nm wavelength light.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.348-349
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• 2007

This paper describes the electrical characteristics of polycrystalline (poly) 3C-SiC thin film diodes, in which poly 3C-SiC thin films on n-type and p-type Si wafers, respectively, were deposited by APCVD using HMDS, Hz, and Ar gas at $1180^{\circ}C$ for 3 hr. The schottky diode with Au/poly 3C-SiC/Si(n-type) structure was fabricated. Its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) values were measured as 0.84 V, over 140 V, 61nm, and $2.7\;{\times}\;10^{19}\;cm^3$, respectively. The p-n junction diodes fabricated on the poly 3C-SiC/Si(p-type) were obtained like characteristics of single 3C-SiC p-n junction diodes. Therefore, poly 3C-SiC thin film diodes will be suitable microsensors in conjunction with Si fabrication technology.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.737-743
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• 1995

Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.306-316
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• 2016

In this paper, an NMOS-diode eFuse OTP (One-Time Programmable) memory cell is proposed using a parasitic junction diode formed between a PW (P-Well), a body of an isolated NMOS (N-channel MOSFET) transistor with the small channel width, and an n+ diffusion, a source node, in a DNW (Deep N-Well) instead of an NMOS transistor with the big channel width as a program select device. Blowing of the proposed cell is done through the parasitic junction formed in the NMOS transistor in the program mode. Sensing failures of '0' data are removed because of removed contact voltage drop of a diode since a NMOS transistor is used instead of the junction diode in the read mode. In addition, a problem of being blown for a non-blown eFuse from a read current through the corresponding eFuse OTP cell is solved by limiting the read current to less than $100{\mu}A$ since a voltage is transferred to BL by using an NMOS transistor with the small channel width in the read mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.734-740
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• 2003

In this paper, A Vector Modulator based a wideband analog phase shifter is realized with four P-I-N diode attenuators, an asymmetric coupled line coupler, a symmetric coupled line coupler, and a power combiner. Simple configuration to have advantages in cost, size, power, and the number of passive circuits is presented. The phase variation due to phase and amplitude error of a P-I-N diode attenuator is derived and used to optimize the overall circuit. The phase shifter shows a total phase shift of 360$^{\circ}$, a 8.2$^{\circ}$maximum phase error, and a 16${\pm}$2.5 dB insertion loss over the wide frequency range of 1 GHz to 3 GHz.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.387-392
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• 2018

Static characteristics of SiC (silicon carbide) lateral p-i-n diodes implemented on semi-insulating substrate without an epitaxial layer are inVestigated. On-axis SiC HPSI (high purity semi-insulating) and VDSI (Vanadium doped semi-insulating) substrates are used to fabricate the lateral p-i-n diode. The space between anode and cathode ($L_{AC}$) is Varied from 5 to $20{\mu}m$ to inVestigate the effect of intrinsic-region length on static characteristics. Maximum breakdown Voltages of HPSI and VDSI are 1117 and 841 V at $L_{AC}=20{\mu}m$, respectiVely. Due to the doped Vanadium ions in VDSI substrate, diffusion length of carriers in the VDSI substrate is less than that of the HPSI substrate. A forward Voltage drop of the diode implemented on VDSI substrate is 12 V at the forward current of $1{\mu}A$, which is higher than 2.5 V of the diode implemented on HPSI substrate.