• 한국전기전자재료학회논문지
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• 제33권2호
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• pp.109-113
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• 2020

A power device is a component used as a switch or rectifier in power electronics to control high voltages. Consequently, power devices are used to improve the efficiency of electric-vehicle (EV) chargers, new energy generators, welders, and switched-mode power supplies (SMPS). Power device designs, which require high voltage, high efficiency, and high reliability, are typically based on MOSFET (metal-oxide-semiconductor field-effect transistor) and IGBT (insulated-gate bipolar transistor) structures. As a unipolar device, a MOSFET has the advantage of relatively fast switching and low tail current at turn-off compared to IGBT-based devices, which are built on bipolar structures. A superjunction structure adds a p-base region to allow a higher yield voltage due to lower R_DS (on) and field dispersion than previous p-base components, significantly reducing the total gate charge. To verify the basic characteristics of the superjunction, we worked with a planar type MOSFET and Synopsys' process simulation T-CAD tool. A basic structure of the superjunction MOSFET was produced and its changing electrical characteristics, tested under a number of environmental variables, were analyzed.

• 한국전기전자재료학회논문지
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• 제27권8호
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.

• 전자공학회논문지A
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• 제33A권10호
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• pp.130-138
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• 1996

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.

• ETRI Journal
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• 제38권2호
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• pp.244-251
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• 2016

In this paper, we investigate the electrical characteristics of two trench-gate-type super-barrier rectifiers (TSBRs) under different p-body implantation conditions (low and high). Also, design considerations for the TSBRs are discussed in this paper. The TSBRs' electrical properties depend strongly on their respective p-body implantation conditions. In the case of the TSBR with a low p-body implantation condition, it exhibits MOSFET-like properties, such as a low forward voltage ($V_F$) drop, high reverse leakage current, and a low peak reverse recovery current owing to a majority carrier operation. However, in the case of the TSBR with a high p-body implantation condition, it exhibits pn junction diode.like properties, such as a high $V_F$, low reverse leakage current, and high peak reverse recovery current owing to a minority carrier operation. As a result, the TSBR with a low p-body implantation condition is capable of operating as a MOSFET, and the TSBR with a high p-body implantation condition is capable of operating as either a pn junction diode or a MOSFET, but not both at the same time.

• 한국진공학회지
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• 제17권2호
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• pp.156-159
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• 2008

Pseudo-MOSFET 방법을 이용하여 Ge농도에 따른 SiGe-on-Insulator(SGOI) 기판의 특성을 평가하였다. SGOI 기판은 compressive-SiGe / Relaxed-Si / Buried oxide / Si-substrate 구조로 SOI 기판 위에 에피택셜 성장법으로 SiGe층을 형성하였으며 compressive SiGe층의 Ge 농도는 각각 16.2％, 29.7％, 34.3％, 56.5％ 이다. 실험결과 Ge 농도가 증가함에 따라 누설전류가 증가하는 특성을 보였으며 threshold voltage는 nMOSFET의 경우 3V에서 7V로 이동하였으며 pMOSFET의 경우도 -7 V에서 -6 V로 이동하는 특성을 보였다. 급속 열처리 공정 (rapid thermal anneal) 후에 매몰 산화층과 기판 계면간의 스트레스에 의한 포획준위가 발생하여 소자특성이 열화되었지만, $H_2/N_2$ 분위기에서 후속 열처리 공정 (post RTA anneal) 을 통하여 계면 간의 포획준위를 감소시켜 SGOI Pseudo-MOSFET의 전기적 특성이 개선되었다.

• 전력전자학회논문지
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• 제4권2호
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• pp.152-158
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• 1999

IGBT는 전압정격 및 전류정격이 높고 도통손실이 낮아서 스위칭 전원장치에 많이 쓰이고 있는 추세에 있다. 그러나 IGBT는 MOSFET에 비해 스위칭 특성이 좋지 않아서 스위칭 손실이 많이 발생하며 주파수에도 제한을 받는다. 본 논문에서는 IGBT와 MOSFET의 장점을 살리기 위하여 IGBT에 MOSFET를 병렬로 접속한 IGBT-MOSFET 병렬 스위치를 사용한 2.4kW, 48V 출력의 고효율 반브리지 직류-직류 변환기를 제안한다. 병렬 스위치에서 주 스위칭 소자인 IGBT는 도통구간에서 주된 역할을 하며 MOSFET는 스위칭시에 주된 역할을 한다. 스위칭 손실을 분석하기 위하여 선형화 모델을 사용하였으며 시뮬레이션을 통하여 변환기의 동작을 확인하였다.

• 대한전자공학회논문지
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• 제19권1호
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• pp.9-13
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• 1982

본실험에서는 N형 Si기판 내부에 P+소오스, 드레인 영역동 마련하고 게이트전극으로서는 PH₃ 를 첨가한 구조로서 Poly-Si gate MOSFET를 제작하여 이에 대한 잡음 특성에 관해 고찰하였다. 실험결과 게이트 면적이 일정하고 막두께가 비교적 두꺼울때는 W/L비 1이상에서는 잡음이 정감되는 경향으로 대체로 이론에 일치하지만 1이하에서는 막두께에 따른 변화는 완만하다는 것이 실증되었다.

• E2M - 전기 전자와 첨단 소재
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• 제10권1호
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 C
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• pp.1550-1552
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• 2003

고밀도의 트렌치 전력 MOSFET를 제작하는 데 있어서 새로운 소자의 구조와 공정을 제시하고 이차원 소자 및 공정 시뮬레이터를 이용하여 검증했다. 트렌치 게이트 MOSFET의 온-저항을 낮추기 위해 셀 피치가 서브-마이크론으로 발전할 경우 문제가 되는 소오스 영역을 확보하고자 p-base의 음 접촉을 위한 P+ 영역과 N+ 소오스 등이 트렌치의 측벽에 형성되고, 트렌치 게이트는 그 아래에 매몰된 구조를 제안했다. 시뮬레이션 결과는 항복전압이 45 V이고, 온-저항이 12.9m${\Omega}{\cdot}mm^2$로 향상된 trade-off 특성을 보였다.

• 한국전기전자재료학회논문지
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• 제29권4호
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• pp.199-204
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• 2016

This paper was proposed floating island power MOSFET for lowering on state resistance and the proposed device was maintained 600 V breakdown voltage. The electrical field distribution of floating island power MOSFET was dispersed to floating island between P-base and N-drift. Therefore, we designed higher doping concentration of drift region than doping concentration of planar type power MOSFET. And so we obtain the lower on resistance than on resistance of planar type power MOSFET. We needed the higher doping concentration of floating island than doping concentration of drift region and needed width and depth of floating island for formation of floating island region. We obtained the optimal parameters. The depth of floating island was $32{\mu}m$. The doping concentration of floating island was $5{\times}1,012cm^2$. And the width of floating island was $3{\mu}m$. As a result of designing the floating island power MOSFET, we obtained 723 V breakdown voltage and $0.108{\Omega}cm^2$ on resistance. When we compared to planar power MOSFET, the on resistance was lowered 24.5% than its of planar power MOSFET. The proposed device will be used to electrical vehicle and renewable industry.