• 한국세라믹학회지
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• 제43권6호
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• pp.362-368
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• 2006

Epitaxial $Ba_{0.5}Sr_{0.5}TiO_3$ (BSTO) thin films have been grown on TiN buffered Si (001) substrates by Pulsed Laser Deposition (PLD) method and the effects of substrate temperature and oxygen partial pressure during the deposition on their dielectric properties and crystallinity were investigated. The crystal orientation, epitaxy nature, and microstructure of oxide thin films were investigated using X-Ray Diffraction (XRD) and Transmission Electron Microscopy (TEM). Thin films were prepared with laser fluence of $4.2\;J/cm^2\;and\;3\;J/cm^2$, repetition rate of 8 Hz and 10 Hz, substrate temperatures of $700^{\circ}C$ and ranging from $350^{\circ}C\;to\;700^{\circ}C$ for TiN and oxide respectively. BSTO thin-films were grown on TiN-buffered Si substrates at various oxygen partial pressure ranging from $1{\times}10^{-4}$ torr to $1{\times}10^{-5}$ torr. The TiN buffer layer and BSTO thin films were grown with cube-on-cube epitaxial orientation relationship of $[110](001)_{BSTO}{\parallel}[110](001)_{TiN}{\parallel}[110](001)_{Si}$. The crystallinity of BSTO thin films was improved with increasing substrate temperature. C-axis lattice parameters of BSTO thin films, calculated from XRD ${\theta}-2{\theta}$ scans, decreased from 0.408 m to 0.404 nm and the dielectric constants of BSTO epitaxial thin films increased from 440 to 938 with increasing processing oxygen partial pressure.

• 한국진공학회지
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• 제7권4호
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• pp.348-354
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• 1998

기판에 대한 열에칭이 에피층에 미치는 영향을 조사하기 위하여 ZnTe 에피층을 hot wall epitaxy(HWE)에 의하여 기판 온도 450~$630^{\circ}C$에서 GaAs(100) 기판 위에 성장하여 에 피층에 대한 이중 결정 요동 곡선(DCRC)과 광발광(PL)을 측정하였다. ZnTe 에피층의 DCRC의 반치폭은 GaAs 기판의 열에칭 온도가 $510^{\circ}C$와 $590^{\circ}C$일 때 가장 작았다. 그러나 $550^{\circ}C$근처에서 반치폭 값들은 표면 원자들의 재구성에 의하여 증가하였다. 그리고 $490^{\circ}C$이 하의 열에칭 온도에서는 산화막에 의하여 반치폭은 증가하였고, 또 $610^{\circ}C$이상에서는 표면 결함에 의하여 증가하였다. PL로부터 가벼운 양공 자유엑시톤 S1,lh과 2차 공명 라만선의 반 치폭은 $550^{\circ}C$ 근처에서 증가하였다. 열에칭 온도가 증가함에 따라 Y-band의 세기와 GaAs 위의 산화막에 관련된 산소에 속박된 자유엑시톤(OBE) 피크의 세기는 일반적으로 감소하였 다. 이러한 실험적인 결과로부터 GaAs 기판의 열에칭은 ZnTe 에피층에 영향을 주는 것으 로 확인되었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.252.2-252.2
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• 2013

ZnO nanostructures have a lot of interest for decades due to its varied applications such as light-emitting devices, power generators, solar cells, and sensing devices etc. To get the high performance of these devices, the factors of nanostructure geometry, spacing, and alignment are important. So, Patterning of vertically- aligned ZnO nanowires are currently attractive. However, many of ZnO nanowire or nanorod fabrication methods are needs high temperature, such vapor phase transport process, metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy, thermal evaporation, pulse laser deposition and thermal chemical vapor deposition. While hydrothermal process has great advantages-low temperature (less than $100^{\circ}C$), simple steps, short time consuming, without catalyst, and relatively ease to control than as mentioned various methods. In this work, we investigate the dependence of ZnO nanowire alignment and morphology on si substrate using of nanosphere template with various precursor concentration and components via hydrothermal process. The brief experimental scheme is as follow. First synthesized ZnO seed solution was spun coated on to cleaned Si substrate, and then annealed $350^{\circ}C$ for 1h in the furnace. Second, 200nm sized close-packed nanospheres were formed on the seed layer-coated substrate by using of gas-liquid-solid interfacial self-assembly method and drying in vaccum desicator for about a day to enhance the adhesion between seed layer and nanospheres. After that, zinc oxide nanowires were synthesized using a low temperature hydrothermal method based on alkali solution. The specimens were immersed upside down in the autoclave bath to prevent some precipitates which formed and covered on the surface. The hydrothermal conditions such as growth temperature, growth time, solution concentration, and additives are variously performed to optimize the morphologies of nanowire. To characterize the crystal structure of seed layer and nanowires, morphology, and optical properties, X-ray diffraction (XRD), field emission scanning electron microscopy (FE-SEM), Raman spectroscopy, and photoluminescence (PL) studies were investigated.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.100-100
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• 2003

본 연구에서는 Si에 Mn을 첨가한 Si$_{l-x}$Mn$_{x}$ 박막의 전기적 및 자기적 특성을 조사하였다. Si$_{l-x}$Mn$_{x}$ 박막은 MBE(Molecular Beam Epitaxy)를 이용하여 native oxide층을 제거하지 않은 (100)Si wafer 위에 성장하였다. Substrate 온도는 50$0^{\circ}C$로 하였으며, 첨가한 Mn 농도는 20%에서부터 80%까지였다. 전기적 특성은 Hall, 4-point probe를 통하여 측정하였고, 자기적 특성은 VSM, FMR, SQUID을 이용하여 측정하였다. 상 분석은 XRD, TEM을 이용하여 관찰하였다 Si$_{l-x}$Mn$_{x}$ 박막은 Hall 측정 결과 상온에서 P-type carrier를 가지며, 비저항은 반도체 영역인 7.6$\times$$10^{-4}$~4.2$\times$$10^{-2}$(ohm-cm)의 값을 가진다. 상온 VSM, 측정결과 Mn의 양이 52% 첨가 시 포화 자화 값이 가장 높은 40emu/cc를 가지며, Mn의 양이 증가할수록 포화 자화 값이 증가하다 다시 감소하는 경향을 가진다. FMR, SQUID 측정에서도 이러한 경향을 확인할 수 있었다 특히, SQUID 분석 결과 두 개 이상의 자성 상이 존재하는 것을 관찰할 수 있었다. XRD, TEM 관찰결과, Si$_{l-x}$Mn$_{x}$은 poly crystal로 성장하였으며, Mn 농도에 따라 여러 상들이 관찰되었다.따라 여러 상들이 관찰되었다.

• 한국진공학회지
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• 제11권1호
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• pp.16-21
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• 2002

$Si_2H_6$가스를 이용한 LPCVD내에서의 실리콘의 선택적 에피텍시 성장을 $1000^{\circ}C$ 이하의 초청정 분위기하의 저온에서 수행하였다. HCI 첨가없이 초청정 공정으로 인한 양질의 에피텍시 Si층이 균일하게 얻어 졌으며, $SiO_2$위에 증착된 실리콘의 잠복기를 발견할 수 있었다. 단결정위의 에피텍시 층은 산화물 층위 보다 더 두껍게 증착되었다. 산소첨가로 잠복기가 20~30초간 증가하였다. 증착된 박막의 절단면과 표면 형상은 SEM으로 관찰되었으며, XRD를 통해 막질을 평가하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.150-151
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• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.

• Advances in Energy Research
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• 제3권2호
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• pp.117-124
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• 2015

In this paper, we have reported an enhancement in thermoelectric properties of un-doped zinc oxide (ZnO) grown by molecular beam epitaxy (MBE) on silicon (001) substrate by annealing treatment. The grown ZnO thin films were annealed in oxygen environment at $500^{\circ}C-800^{\circ}C$, keeping a step of $100^{\circ}C$ for one hour. Room temperature Seekbeck measurements showed that Seebeck coefficient and power factor increased from 222 to $510{\mu}V/K$ and $8.8{\times}10^{-6}$ to $2.6{\times}10^{-4}Wm^{-1}K^{-2}$ as annealing temperature increased from 500 to $800^{\circ}C$ respectively. This observation was related with the improvement of crystal structure of grown films with annealing temperature. X-ray diffraction (XRD) results demonstrated that full width half maximum (FWHM) of ZnO (002) plane decreased and crystalline size increased as the annealing temperature increased. Photoluminescence study revealed that the intensity of band edge emission increased and defect emission decreased as annealing temperature increased because the density of oxygen vacancy related donor defects decreased with annealing temperature. This argument was further justified by the Hall measurements which showed a decreasing trend of carrier concentration with annealing temperature.

• 한국전기전자재료학회논문지
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• 제32권3호
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.