• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.69-76
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• 2006

This paper proposes a self-repair system which is able to self-repair in cell unit by imitating the structure of living beings. Because the data of artificial cells move even diagonally, our system can self-repair faults not in column unit, but in cell unit. It leads to design an efficient self-repair system for multiple faults. Moreover, in artificial cell design, the usage of logic-based design method has smaller system size than that of the previous register-based design method. Our experimental result for 2-bit up/down counter shows 40.3% reduction in hardware overhead, compared to the previous method [6].

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.159-159
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• 2004

With the increasing number of subscribers in the mobile communication, the reduction of the cell size and the increment of roaming frequency have increased the cost of location management. In order to reduce the cost of location management, we propose a new strategy of location management. In this scheme, whether the terminal executes location update or not is decided both by the call arrival probability in a new LA and by the number of location updates which are unexecuted despite that the terminal moved into a new LA. The call arrival probability is computed using the predicted information about the terminal mobility pattern. We simulated to evaluate our strategy's performance. In the high mobility prediction level, this scheme reduces the cost of location update considerably. Even though it is in the low mobility prediction level, the cost does not exceed that of IS-41 at most. This scheme also showed better performance, compared with that of AS(Alternative Strategy) which requires an overhead such as predicted information maintenance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.1-8
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• 2004

With the increasing number of subscribers in the mobile communication, the reduction of the cell size and the increment of roaming frequency have increased the cost of location management. In order to reduce the cost of location management, we propose a new strategy of location management. In this scheme, whether the terminal executes location update or not is decided both by the call arrival probability in a new LA and by the number of location updates which are unexecuted despite that the terminal moved into a new LA. The call arrival probability is computed using the predicted information about the terminal mobility pattern. We simulated to evaluate our strategy's performance. In the high mobility prediction level, this scheme reduces the cost of location update considerably. Even though it is in the low mobility prediction level, the cost does not exceed that of IS-41 at most. This scheme also showed better performance, compared with that of AS(Alternative Strategy) which requires an overhead such as predicted information maintenance.

• Journal of IKEEE
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• v.14 no.1
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• pp.8-16
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• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.

• The KIPS Transactions:PartC
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• v.9C no.4
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• pp.473-480
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• 2002

Although many researches on IDS (Intrusion Detection System) have been performed, the most of them are limited to the algorithm of detection software. However, even an IDS with superior algorithm can not detect intrusion, if it loses packets which nay have a clue of intrusions. In this paper, we suggest an efficient wav to improve the performance of IDS by reducing packet losses occurred due to hardware limitation and abundant processing overhead introduced by massive detection software itself. The reduction in packet losses is achieved by dropping hacking-free packets. The result shows that this decrease of packet losses leads an IDS to improve the detection rate of real attack.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.12
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• pp.2272-2293
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• 2011

Communication technology of future networks is predicted to provide a large variety of services including WiFi service in vehicular network. In this paper, we assume that vehicles are embedded with WiMAX antenna and in-vehicle terminals receive WiMAX traffic through WiFi interface. This assumption will impose severe performance degradation due to interference among mobile BSSs when WiFi access points (APs) are densely located. Existing interference avoidance techniques cannot properly resolve the above problems and do not cope with dynamically moving vehicular scenario since they focus only on the fixed network topology. In this paper, we propose a mobility-aware interference avoidance scheme for WiFi services. The proposed scheme computes the interference duration by exploiting mobility vector and location information of neighboring APs. If the interference duration is not negligible, our scheme searches for another channel in order to avoid interference. However, if the interference duration is negligible, our scheme continues to use the channel to reduce switching overhead. To measure the effectiveness of the proposed scheme against other existing techniques, we evaluated performance by using OPNET simulator. Through the simulation, we obtained about 60% reduction in the maximum interference frequency and about 67% improvement in throughput. Furthermore, our scheme provides fair channel usage.

• Journal of Korean Society of Environmental Engineers
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• v.34 no.6
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• pp.382-390
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• 2012

Global warming has been hot issue world wide. Korea has been dealing with the global issue under the slogan of low carbon and green-growth such as setting national greenhouse gas (GHG) reduction targets and allocation to each industrial sector. Infrastructure construction, in which enormous social overhead capital (SOC) is input, has great role as one of the actions. Road is one of the representative infrastructure and large amount of resources is utilized in its construction, operation and maintenance stage. The estimation methodology of life cycle carbon emissions was developed and applied to a case study of highway currently under construction in this study. Also, total carbon emissions of all the highway in South Korea at present (2009) and cumulative carbon emissions from 2009 to 2020 were estimated using the results of case study.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.4
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• pp.29-37
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• 2013

Multiplayer games typically organized based on a client-server(CS) or peer-to-peer(PP) architecture. The CS architecture is not scalable with the number of players due to a large bandwidth requirement at the server. The PP architecture, on the other hand, introduces significant overhead for the players, as each player needs to check the consistency between its local state and the state of all other players. We then propose a method that combines the merits of CS and PP. In this method, players exchange updates with lower priority in a peer-to-peer manner but communicate directly with a central server for the other updates. As a result, the proposed method has a lower network bandwidth requirement than the server of a CS architecture and the server bandwidth bottleneck is removed. For another important issue about multiplayer games, this method always maintains state consistency among players correctly. The performance of this method is evaluated through extensive simulation experiments and analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.