• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.29-36
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• 2004

A flexible packaging scheme, which includes chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending tests and finite element analysis. Thinned silicon chips (t<30 $\mu\textrm{m}$) are fabricated by chemical etching process to avoid possible surface damages on them. And the chips are stacked directly on $Kapton^{Kapton}$film by thermal compressive bonding. The low height difference between the thinned silicon chip and $Kapton^{Kapton}$film allows electroplating for electrical interconnection method. Because the 'Chip' is embedded in the flexible substrate, higher packaging density and wearability can be achieved by maximized usable packaging area.

• International Journal of Precision Engineering and Manufacturing
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• v.6 no.3
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• pp.24-28
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• 2005

Stress state of chip formation zone is one of the main problems in metal cutting mechanics. In two-dimensional case this process is usually considered as consistent shears of work material along one of several shear surfaces, separating chip from workpiece. These shear planes are assumed to be trajectories of maximum shear stress forming corresponding slip-line field. This paper suggests a new approach to the constriction of slip-line field, which implies uniform compression in chip formation zone. Based on the given model it has been found that imaginary shear line in orthogonal cutting is close to the trajectory of maximum normal stress and the problem about its determination has been considered as well. It has been shown that there is a second central slip-line field inside chip, which corresponds well to experimental data about stress distribution on tool rake face and tool-chip contact length. The suggested model would be useful in understanding mechanistic problems in machining.

• Resources Recycling
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• v.6 no.4
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• pp.24-30
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• 1997

The recent trend of recycle of mold scrap is to make high quality secondary ingot which can be used as raw malerial undcr intensive control of scrap. In this study, recycle of aluminum chlp generated atter machinmg process of castings was performed by vortex melting melhod Vortex melting technique was adopted for chip mclting process. The condition far optimal vortcx depth was decided using water mndellng experiment varying the shape, location, rotating speed of stlircr and watcr levcl. Before melting, chips were preheated at room temperame, 200, 300, $ 400^{\circ}C$and then submerged in the mirldle of vortex. The lecovery rale depending on the temperature was examined. As a result vortex depth was influenccd only by shape and rotating speed of stirrer, and the hlghest recovery rate oI 97% was obta~nedw hcn the submerged chip was preheated at $300^{\circ}C.$

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.86-93
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• 2010

A system-on-chip (SoC) includes more functions and requires rapidly increased data bandwidth as the development of semiconductor process technology and SoC design methodology. As a result, the data bandwidth of on-chip-networks in SoCs becomes a key factor of the system performance, and the research on the on-chip-network is performed actively. Either AXI or OCP is considered to a substitute of the AHB which has been the most popular on-chip-network. However, they have much increased number of signal wires, which make it difficult to design the interface logic and the network hardware. The compatibility of the protocols with other protocols is not so good. In this paper, we propose a new interface protocol for on-chip-networks to improve the problems mentioned above. The proposed protocol uses less number of signal wires than that of the AHB and considers the compatibility with other interface protocols such as the AXI. According the analysis results, the performance of the proposed protocol per wire is much better than that of the AXI although the absolute performance is slightly inferior.

• KSBB Journal
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• v.20 no.3
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• pp.197-204
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• 2005

Lab-on-a-chip is a miniaturized analytical device in which all of the procedures for the analysis of molecules are carried out, such as pretreatment, reaction, separation, detection, etc. Lab-on-a-chip has increasing concern as a device not only for rapid detection of molecules but also for high throughput screening and point of care, because conventional laborious and time consuming analytical procedures can be substituted. Thus, a lot of microfabrication and analytical techniques for lab-on-a-chip have been developed with microstructures smaller than a few hundreds of micrometers. Separation of the molecules is one of the most important components of lab-on-a-chip, because effective separation method can simplify the design and can provide better sensitivity. The electrokinetic separation based on capillary electrophoresis is most widely employed technique in lab-on-a-chip for the control of fluids and the separation of molecules. In this article, bioseparation techniques and its applications realized in lab-on-a-chip are reviewed.

• Korean Journal of Organic Agriculture
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• v.10 no.4
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• pp.69-78
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• 2002

This experiment was conducted to investigate the changes of sugar contents and chip color during 104days storage after harvesting of five potato varieties. The potato varieties were planted on 1st April in 1999 and harvested on 10. July in 1999. $No_2$ contents in potato petiole tended to decrease repidly at tuber maturing stage. $K^+$ contents in potato petiole tended to in crease at 70 days ofter planting on medium maturing varieties, and at 90 days after planting on late maturing variety. Snowden variety was no desirable cultivar for processing on spring cultivation due to long growth period. Contents of solid and sugar in potatoes affected on potato chip color. Higher contents of solid in potato varieties showed low sugar contents and no change on chip color during storage.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.4
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• pp.40-46
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• 1998

Leakage phenomena of flip-chip structures on common GaAs and alumina main substrates are characterized using the spectral domain approach to reduce the possible chip-to-chip crosstald and transmission resonance. We have found taht the longitudinal section magnetic mode is dominant for the coplanar waveguide leakage andthe leakage can be suppreassed by properly managing the gap height and the main substrate thickness in addition to the dielectric constant. These calculation results will be helpful for designing and flip-chip packagaing of high-frequency integrated circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.161-172
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• 1994

This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.

• Journal of IKEEE
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• v.23 no.4
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• pp.1203-1207
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• 2019

As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included in on-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitration result by combining multiple routers. Allocating desired bandwidths to the ports across the routers is more difficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed to overcome the limitations of existing local arbitration policies. Each IP can control the priority of a packet depending on the data communication requirement within the allocated bandwidth. The experimental results show that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple router on-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.