• 전자공학회논문지
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• 제49권9호
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• pp.259-269
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• 2012

전원 전압이 낮아지고, 칩의 동작 속도가 빨라짐에 따라 온-칩 인덕턴스를 포함한 power distribution network (PDN) 분석이 중요해 질 것으로 예측된다. 본 논문에서는 일반적인 온-칩 전력 격자 구조에 적용시킬 수 있는 효과적인 인덕턴스 추출방법에 대해 제안한다. Chip layout에 적용할 수 있는 loop 인덕턴스 모델을 제시하고, 그 모델을 사용하여 post layout RC extraction netlist로 부터 인덕턴스를 포함한 netlist를 추출할 수 있는 tool을 개발하였다. 제안된 loop 인덕턴스 모델과 개발된 tool의 정확성은 회로 simulation을 통해 PEEC 모델과 비교하여 검증하였다. 인덕턴스 추출 방법을 실제 chip layout에 적용시켜 on-chip inductance를 포함한 PDN의 voltage fluctuation을 예측하였다. 패키지와 PCB 모델을 포함한 co-simulation 모델을 구성하여 on-chip inductance의 영향을 분석하였다.

• 대한기계학회논문집
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• 제17권12호
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• pp.2926-2935
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• 1993

Chip breaker selection analysis, only being possible through experimental process, was obtained by a applied equation which used an orthogonal cutting model and a basic chip deformation. This equation could present an analysis of the chip breaking phenomena without the use of an actual experimetal method, and it was applied to computer simulation and proved the validity of theory through actual experiments. From these results, an efficient method for finding the optimum conditions of chip breaking was found through an optimized theory being applied to basic program. A finite element model for simulating chip breaking in orthogonal cutting was developed and discussed. By simulation the animation of chip breaking is observed in process on the computer screen.

• 반도체디스플레이기술학회지
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• 제14권3호
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• 한국안전학회지
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• 제9권4호
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• pp.17-28
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• 1994

Chip breaking is important in lathe work for maintaining good surface of the products and safety of operator. The purpose of this study is to investigate the performance of chip breaking and chip shape resulted from the carbide inserts with grooved type and obstruction type chip breaker. Experiments have been performed under the following cutting conditions, (1) constant cutting speed with variable depth of cut and feed rate, (2) constant depth of cut with variable cutting speed and feed rate. Also, the flying distance of chip and it's distribution have been investigated. As a results, good performance of chip breaking can be obtained for small radius of curvature and land width of grooved type chip breaker. And the thickness of chip increase with the increase of feed rate and decrease of cutting speed, and the chip breaking becomes easier with the increase of chip thickness due to the large deformation rate. Obstraction type chip breaker shows better performance of surface roughness than the grooved type. The flying distance of the chips over 90% are less than 1 meter, and the distance decreases as the feed rate decreases.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• 한국생산제조학회지
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• 제9권3호
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• pp.48-54
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• 2000

In this study the characteristics of chip formation of the cold drawn Bi-S free machining steels were assessed. And for comparison those of the cold drawn Pb-S free machining steel the hot rolled low carbon steel which has MnS as free machining inclusions and the conventional steels were also investigated. During chip formation the cold drawn free machining steels show relatively little change in thickness and width of chip compare to those of the conventional carbon steels. And a single parameter which indicates the degree of deformation during chip formation chip cross-section area ratio is introduced. The chip cross-section area ratio is defined as chip cross-section area is divided by undeformed chip cross-section area. The variational patters of the chip cross-section area ratio of the materials cut are similar to those of the shear strain values. The shear stress however seems to be dependent on the carbon content of the materials. The cold drawn Bi-S and Pb-S steels show nearly the same chip forming behaviors and the energy consumed during chip formation is almost same. A low carbon steel without free machining aids shows poor chip breakability due to its high ductility. By introducing a small amount of free machining inclusions such as MnS Bi, Pb or merely increasing carbon content the chip breakability improves significantly.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1995년도 추계학술대회 논문집
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• pp.271-275
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• 1995

Chip control is a major problem in automatic machining process, especially in finish operation. Chip breaker is one of the important factors to be determined for the scheme of chip control. As unbroken chips are grown, there deteriorate quality of the surface roughness and process automation can be carried out. In this study, to get rid of chip curling problem while turning internal hole, optimal chip breaker is selected form the experiment. The experiment is planned with Taguchi's method that is based on the orthogonal arrary of design factor. From the respose table, cutting speed, feedrate, depth of cut, and tool geometry are major factors affecting chip formation. Then, optmal chip breaker is selected and this is verified good enough for chip control from the experiment.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1999년도 추계학술대회 논문집 - 한국공작기계학회
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• pp.351-356
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• 1999

In this study, the characteristics of chip formation of the cold drawn Bi-S free machining steels were assessed. And for comparison, those of the cold drawn Pb-S free machining steel, the hot rolled low carbon steel which has MnS as free machining inclusions and the conventional steels were also investigated. During chip formation, the cold drawn free machining steels show relatively little change in thickness and width of chip compare to those of the conventional carbon steels. And a single parameter which indicates the degree of deformation during chip formation, 'chip cross-section area ratio' is introduced. The chip cross-section area. The variational patterns of cross-section area is divided by undeformed chip cross-section area. The variational patterns of the chip cross-section area ratio of the materials cut are similar to those of the shear strain values. The shear stress, however, seems to be dependent on the carbon content of the materials. The cold drawn BiS and Pb-S steels show nearly the same chip forming behaviors and the energy consumed during chip formation is almost same. A low carbon steel without free machining aids shows poor chip breakability due to its high ductility. By introducing a small amount of non-metallic inclusions such as MnS, Bi, Pb or merely increasing carbon content the chip breakability improves significantly.

• 한국전자파학회논문지
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• 제24권12호
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• pp.1120-1127
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• 2013

본 논문에서는 칩온웨이퍼(Chip on Wafer: CoW) 공정기술을 이용한 새로운 칩온칩(Chip on Chip: CoC) 플립칩 범프 구조들을 제안하여 설계, 제작하고, 초고주파 영역에서의 응답 특성을 분석하였다. Cu 필러(Pillar)/SnAg, Cu 필러/Ni/SnAg의 기존 범프들, 그리고 SnAg, Cu 필러/SnAg, Cu 필러/Ni/SnAg를 Polybenzoxazole(PBO)로 보호한 새로운 범프들을 구성하여 웨이퍼의 $2^{nd}$ Polyimide(PI2) 층의 도포 유무에 따라 10가지 형태의 CoC 샘플들을 구조 설계하였고, 20 GHz까지의 주파수 특성이 고찰되었다. 측정 결과를 고려할 때 PI2 층이 도포된 소자들이 본 실험에 사용된 배치 플립칩 공정에 더 적합함을 알 수 있었고, 18 GHz에서 평균 0.14 dB의 삽입 손실을 보였다. 미세 패드 간격을 가지는 칩의 패키지 용도로 새로 개발된 범프들의 삽입 손실(0.11~0.14 dB)은 기존 범프들의 삽입 손실(0.13~0.17 dB)과 비교해 18 GHz까지 유사한 성능을 보이거나, 다소 좋은 특성을 보여 높은 집적도를 요구하는 다양한 초고주파 패키지에 활용될 수 있음이 확인되었다.