• Journal of electromagnetic engineering and science
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• v.4 no.3
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• pp.137-142
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• 2004

In this paper, we present a new current-current negative feedback(CCNF) differential voltage-controlled oscillator (VCO) with 1/f induced low-frequency noise suppressed. By means of the CCNF, the 1/f induced low-frequency noise is removed from the proposed CCNF VCO. Also, high-frequency noise is stopped from being down-converted into phase noise by means of the increased output impedance through the CCNF and the feedback capacitor $C_f. The proposed CCNF VCO represents 11-dB reduction in phase noise at 10 kHz offset, compared with the conventional differential VCO. The phase noise of the proposed CCNF VCO is measured as - 87 dBc/Hz at 10 kHz offset frequency from 5.5-GHz carrier. The proposed CCNF VCO consumes 14.0 mA at 2.0 V supply voltage, and shows single-ended output power of - 12 dBm.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.3
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• pp.365-373
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• 2015

The performance of 4-switch 3-phase inverter(FSTPI) is mainly affected by the unbalanced voltages between two capacitors which replace two switches of conventional 6-switch 3-phase inverter(SSTPI). This paper proposes a DC offset current injection method to compensate the capacitor voltage unbalance for FSTPI. A simplified SVPWM method which can be applied to FSTPI is also proposed. The validity of the proposed methods is verified by computer simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.318-325
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• 2008

A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a $0.13\;{\mu}m$ CMOS process. A digital calibration of DC reference voltage is proposed for the $1^{st}$ preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the $2^{nd}$ preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 mW with a 195 MHz $400\;mV_{p-p}$ sine wave input.

• Progress in Superconductivity and Cryogenics
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• v.18 no.2
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• pp.18-20
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• 2016

The study of superconducting fault current limiter (SFCL) is continuously being studied as a countermeasure for reducing fault-current in the power system. When the fault occurred in the power system, the fault-current was limited by the generated impedance of SFCLs. The operational characteristics of the flux-offset type SFCL according to turn ratios between the primary and the secondary winding of a reactor were compared in this study. We connected the secondary core to a superconductor and a SCR switch in series in the suggested structure. The fault current in the primary and the secondary winding of the reactor and the voltage of the superconductor on the secondary were measured and compared. The results showed that the fault current in the load line was the lowest and the voltage applied at both ends of the superconductor was also low when the secondary winding of the reactor had lower turn ratio than the primary. It was confirmed based on these results that the turn ratio of the secondary winding of the reactor must be designed to be lower than that of the primary winding to reduce the burden of the superconductor and to lower the fault current. Also, the suggested structure could increase the duration of the limited current by limiting the continuous current after the first half cycle from the fault with the fault current limiter.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.5
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• pp.431-439
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• 2017

An asymmetric half-bridge is one of the most promising topology in low-power application because of its small number of components and inherent zero-voltage switching capability. However, when it is designed taking into a hold-up time, it has large transformer offset current and small transformer turns-ratio, which severely decreases the total efficiency of s converter. In this paper, a new boost-integrated asymmetric half-bridge converter is proposed to solve these problems. The integrated boost converter compensates the hold-up time, thus facilitating optimal design in nominal state. As a result, the proposed converter can achieve high efficiency in nominal state. To verify the effectiveness of the proposed converter, an experiment is conducted using a 250-400 V input and 45 V/3.3 A output prototype.

• Journal of IKEEE
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• v.23 no.3
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• pp.1020-1026
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• 2019

In this paper, a rotor polarity detection algorithm is proposed to control the single-phase permanent magnet synchronous motors(SP-PMSMs) for high speed sensorless operation. Generally, the sensorless control of a SP-PMSM is switched to the sensorless operation in a specific speed region after the open loop startup. As a result, it is necessary to detect the rotor polarity to maintain a constant rotational direction of the SP-PMSM at the starting process. There, this paper presents a novel rotor polarity detection method using a high frequency voltage signal and offset current which is generated by current regulator. The proposed algorithm verified the effectiveness and usefulness of the rotor polarity detection through several experiments.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2804-2806
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• 1999

This paper presents a voltage regulator for an AC power supply. It is designed to have the band Pass filter characteristic for the system to be free from DC-offset or sub-frequency fluctuation in the output voltage wave

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.327-328
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• 2016

This paper proposes the PLL algorithms with both the quadrature signal generator (QSG) and the positive-sequence calculator (PSC) in order to remove the effects of the three-phase grid voltage with dc offset voltages. The performances of the proposed method are verified with both the simulation result and the experimental result with 32-bit DSP.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.773-775
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• 1998

This paper describes the highly sensitive Si Hall magnetic sensing system which can measure the earth magnetic field. Generally, the important parameters in Hall device which degrade the ability of magnetic detection are offset voltage and 1/f noise. The offset voltage and 1/f noise in Hall plates can be reduced by spinning current method. In this paper, we implement the highly sensitive Si Hall magnetic sensing system using spinning current method. As a result, the minimum detectable magnetic field is 0.1G.