JSTS:Journal of Semiconductor Technology and Science

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A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration

  • Published : 2008.12.30
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Abstract

A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a $0.13\;{\mu}m$ CMOS process. A digital calibration of DC reference voltage is proposed for the $1^{st}$ preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the $2^{nd}$ preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 mW with a 195 MHz $400\;mV_{p-p}$ sine wave input.

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References

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Cited by

  1. 1V 1.6-GS/s 6-bit Flash ADC with Clock Calibration Circuit vol.16, pp.9, 2012, https://doi.org/10.6109/jkiice.2012.16.9.1847