• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.66-74
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• 1995

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.9
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• pp.820-825
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• 2004

In this paper an octave tuning voltage controlled oscillator which is used in set-top TV tuner was designed. Oscillation frequency range is 0.9 GHz～2.2 GHz with 1.3 GHz bandwidth. By using 4 varactor diodes in base and emitter of transistor, wide-band tuning, sweep linearity and low phase noise could be achieved. Designed VCO requires a tuning voltage of 0 V ～ 20 V and DC consumption of 10 V and 15 mA. Designed VCO exhibits an output power of 5.3 dBm $\pm$1.1 dB and a phase noise below -94.8 dBc/Hz ＠ 10 kHz over the entire frequency range. The sweep linearity shows 65 MHz/V with a deviation of $\pm$10 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.64-72
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• 2010

This paper presents a wide range VCO with fine coarse tuning step using a sigma-delta modulation technique for UWB frequency synthesizer. The proposed coarse tuning scheme provides the low effective frequency resolution without any degradation of phase noise performance. With three steps coarse tuning, the VCO has wide tuning range and fine tuning step simultaneously. The frequency synthesizer with VCO was implemented with 0.13 ${\mu}m$ CMOS technology. The tuning range of the VCO is 5.8 GHz~6.8 GHz with the effective frequency resolution of 3.9 kHz. It achieves the measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range 16.8 % with 5.9 mW power. The figure-of-merit with the tuning range is -181.5 dBc/Hz.

• Journal of Navigation and Port Research
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• v.30 no.10 s.116
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• pp.847-853
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• 2006

In this paper, we designed VCO(voltage controlled oscillator} that is composed of a dielectric resonator and a varactor diode, and the PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The results at 12.05 GHz show the output power is 13.54 dBm frequency tuning range approximately +/- 7.5 MHz, and power variation over the tuning range less than 0.2 dB, respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 dBc/Hz at 100 kHz offset from carrier, and The second harmonic suppression is less than -41.49 dBc. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.613-623
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• 2012

In this paper, we present an ultra miniaturized voltage tuned oscillator, with HMIC-type amplifier and phase shifter, using LTCC artificial dielectric resonator. ADR which consists of periodic conductor patterns and stacked layers has a smaller size than a dielectric resonator. The design specification of ADR is obtained from the design goal of oscillator. The structure of the ADR with a stacked circular disk type is chosen. The resonance characteristic, physical dimension and stack number are analyzed. For miniaturization of ADRO, the ADR is internally implemented at the upper part of the LTCC substrate and the other circuits, which are amplifier and phase shifter are integrated at the bottom side respectively. The fabricated ADRO has ultra small size of $13{\times}13{\times}3mm^3$ and is a SMT type. The designed ADRO satisfies the open-loop oscillation condition at the design frequency. As a results, the oscillation frequency range is 2.025~2.108 GHz at a tuning voltage of 0~5 V. The phase noise is $-109{\pm}4$ dBc/Hz at 100 kHz offset frequency and the power is $6.8{\pm}0.2$ dBm. The power frequency tuning normalized figure of merit is -30.88 dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• The Bulletin of The Korean Astronomical Society
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• v.35 no.2
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• pp.60.1-60.1
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• 2010

한국우주전파관측망(Korean VLBI Network, KVN)을 이루는 21m 망원경의 수신기에는 전파세기를 모니터링하기 위한 장치가 있으나, 회로잡음, 이득, 그리고 DC offset 등의 개선을 위하여 전파세기 시험용 측정기를 설계하였다. 이 장치는 입력신호의 전압에 대하여 주파수로 출력되는데, 선형성과 신호잡음특성이 중요하다. 이러한 회로 특성 파악과 개선을 위하여, 차동입력 증폭, 단일입력 증폭, 그리고 1:1앰프출력 등으로 입력신호에 대하여 다양한 실험을 할 수 있게 하였고, 샘플링 주파수도 1 MHz와 4 MHz를 선택할 수 있게 전파세기 시험용 측정기를 설계하였다. 시제품을 제작하여 DC 입력 시험, 0 전압입력 시험, 노이즈 제너레이터를 이용한 동작 시험, 그리고 KVN연세전파천문대의 수신기에 직접 연결한 실험을 통하여, 최종 이득안정도의 잡음스펙트럼 ~1.5 X $10^{-4}\;dG/G(Hz^{-1/2})$@1Hz를 얻었다. 이번 실험 결과를 바탕으로 KVN의 전파세기측정기를 새로 제작할 예정이다. 이에 전파세기 시험용 측정기의 설계 결과를 소개하고자 한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.4 s.95
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• pp.345-350
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• 2005

An X-band push-push VCO for low cost applications is proposed. The designed push-push oscillator achieves a wide tuning range in the X-band by the collector bias tuning instead of extra varactor diodes. The measurement shows a wide tuning bandwidth of $900\;\cal{MHz}\;from\;10.9\;\cal{GHz}\;to\;11.8\;\cal{GHz}$ with a drain bias voltage varying from 4 to 9 V, excellent fudamental suppression of $-30\;\cal{dBc}$ and good phase noise of $-115\;\cal{dBc/Hz}\;@\;1\;\cal{MHz}$ offset.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.