• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.356-363
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• 2014

In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

• Ceramist
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• v.21 no.2
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• Smart Media Journal
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• v.11 no.2
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• pp.77-83
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• 2022

The neuromorphic architecture uses a spiking neural network (SNN) model to derive more accurate results as more spike values are accumulated through inference experiments. When the inference result converges to a specific value, even if the inference experiment is further performed, the change in the result is smaller and power consumption may increase. In particular, in an AI-based IoT environment, power consumption can be a big problem. Therefore, in this paper, we propose a technique to reduce the power consumption of AI-based IoT by reducing the inference time by adjusting the inference image exposure time in the neuromorphic architecture environment. The proposed technique calculates the next inferred image exposure time by reflecting the change in inference accuracy. In addition, the rate of reflection of the change in inference accuracy can be adjusted with a coefficient value, and an optimal coefficient value is found through a comparison experiment of various coefficient values. In the proposed technique, the inference image exposure time corresponding to the target accuracy is greater than that of the linear technique, but the overall power consumption is less than that of the linear technique. As a result of measuring and evaluating the performance of the proposed method, it is confirmed that the inference experiment applying the proposed method can reduce the final exposure time by about 90% compared to the inference experiment applying the linear method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.5
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• pp.71-77
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• 2021

Recently, there is a demand for efficient program development of an IoT application support frameworks considering heterogeneous hardware characteristics. In addition, the scope of hardware support is expanding with the development of neuromorphic architecture that mimics the human brain to learn on their own and enables autonomous computing. However, most existing IoT IDE(Integrated Development Environment), it is difficult to support AI(Artificial Intelligence) or to support services combined with various hardware such as neuromorphic architectures. In this paper, we design an AI component abstract model that supports the second-generation ANN(Artificial Neural Network) and the third-generation SNN(Spiking Neural Network), and implemented an autonomous IoT IDE based on the proposed model. IoT developers can automatically create AI components through the proposed technique without knowledge of AI and SNN. The proposed technique is flexible in code conversion according to runtime, so development productivity is high. Through experimentation of the proposed method, it was confirmed that the conversion delay time due to the VCL(Virtual Component Layer) may occur, but the difference is not significant.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.4
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• pp.311-321
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• 2022

The report reviews recent research efforts in demonstrating a computing system whose operation principle mimics the dynamics of biological neurons. The temporal variation of the membrane potential of neurons is one of the key features that contribute to the information processing in the brain. We first summarize the neuron models that explain the experimentally observed change in the membrane potential. The function of ion channels is briefly introduced to understand such change from the molecular viewpoint. Dedicated circuits that can simulate the neuronal dynamics have been developed to reproduce the charging and discharging dynamics of neurons depending on the input ionic current from presynaptic neurons. Key elements include volatile memristors that can undergo volatile resistance switching depending on the voltage bias. This behavior called the threshold switching has been utilized to reproduce the spikes observed in the biological neurons. Various types of threshold switch have been applied in a different configuration in the hardware demonstration of neurons. Recent studies revealed that the memristor-based circuits could provide energy and space efficient options for the demonstration of neurons using the innate physical properties of materials compared to the options demonstrated with the conventional complementary metal-oxide-semiconductors (CMOS).

• Journal of the Korean institute of surface engineering
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• v.53 no.6
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• pp.330-342
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• 2020

Since the original report on ferroelectricity in Si-doped HfO2 in 2011, fluorite-structured ferroelectrics have attracted increasing interest due to their scalability, established deposition techniques including atomic layer deposition, and compatibility with the complementary-metal-oxide-semiconductor technology. Especially, the emerging fluorite-structured ferroelectrics are considered promising for the next-generation semiconductor devices such as storage class memories, memory-logic hybrid devices, and neuromorphic computing devices. For achieving the practical semiconductor devices, understanding polarization switching kinetics in fluorite-structured ferroelectrics is an urgent task. To understand the polarization switching kinetics and domain dynamics in this emerging ferroelectric materials, various classical models such as Kolmogorov-Avrami-Ishibashi model, nucleation limited switching model, inhomogeneous field mechanism model, and Du-Chen model have been applied to the fluorite-structured ferroelectrics. However, the polarization switching kinetics of fluorite-structured ferroelectrics are reported to be strongly affected by various nonideal factors such as nanoscale polymorphism, strong effect of defects such as oxygen vacancies and residual impurities, and polycrystallinity with a weak texture. Moreover, some important parameters for polarization switching kinetics and domain dynamics including activation field, domain wall velocity, and switching time distribution have been reported quantitatively different from conventional ferroelectrics such as perovskite-structured ferroelectrics. In this focused review, therefore, the polarization switching kinetics of fluorite-structured ferroelectrics are comprehensively reviewed based on the available literature.

• Journal of IKEEE
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• v.28 no.2
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• pp.234-238
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• 2024

This paper presents a study on the integration of 3D-stacked dual-tip RRAM with a CNN accelerator architecture, leveraging its low drive current characteristics and scalability in a 3D stacked configuration. The dual-tip structure is utilized in a parallel connection format in a synaptic array to implement multi-level capabilities. It is configured within a Network-on-chip style accelerator along with various hardware blocks such as DAC, ADC, buffers, registers, and shift & add circuits, and simulations were performed for the CNN accelerator. The quantization of synaptic weights and activation functions was assumed to be 16-bit. Simulation results of CNN operations through a parallel pipeline for this accelerator architecture achieved an operational efficiency of approximately 370 GOPs/W, with accuracy degradation due to quantization kept within 3%.