• 한국정보통신학회논문지
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• 제14권3호
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• pp.754-766
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• 2010

무선 통신 프로토콜에서 하위 계층을 담당하는 부분은 네트워크 디바이스이다. 네트워크 디바이스는 하드웨어/소프트웨어로 구성되기 때문에 시스템-온-칩 시뮬레이터를 이용하여 설계할 수 있다. 하지만 네트워크 디바이스는 다양한 상위 계층 통신 프로토콜과 상호 동작하기 때문에 시스템-온-칩 시뮬레이터뿐 아니라 네트워크 시뮬레이터의 지원이 필요하다. 그러므로 이 두개의 시뮬레이터를 결합하면, 이러한 요구를 만족하는 네트워크 디바이스의 개 발 환경이 될 수 있다. 본 논문에서는 이러한 환경을 제공하는 통합 시뮬레이터를 제안한다. 제안하는 통합 시뮬레이터는, 통합으로 인한 성능 저하가 발생하지 않는다. 또한, 각 시뮬레이터의 커널 구현에 독립적이므로 통합이 용이하다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권4호
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• pp.258-262
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• 2004

Storage over Ethernet (SoE) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike SAN, no server computer intervenes between the storage and the client hosts. We propose a SoE disk controller (SoEDC) amenable to low-cost, single-chip implementation that processes a simplified L3/L4 protocol and converts commands between Ethernet and ATA/ATAPI, while the rest of the complex tasks are performed by the remote hosts. Thanks to simple architecture and protocol, the SoEDC implemented on a single $4mm{\times}4mm$ chip in 0.18um CMOS technology achieves maximum throughput of 55MB/s on Gigabit Ethernet, which is comparable to that of a high-performance disk storage locally attached to a host computer.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제7권4호
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• pp.267-273
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• 2007

This paper presents the implementation of an educational kit for intelligent system control education. Neural network control algorithms are presented and control hardware is embedded to control the inverted pendulum system. The RBF network and the MLP network are implemented and embedded on the DSP 2812 chip and other necessary functions are embedded on an FPGA chip. Experimental studies are conducted to compare performances of two neural control methods. The intelligent control educational kit(ICEK) is implemented with the inverted pendulum system whose movements of the cart is limited by space. Experimental results show that the neural controllers can manage to control both the angle and the position of the inverted pendulum systems within a limited distance. Performances of the RCT and the FEL control method are compared as well.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.505-513
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• 2017

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.

• 대한기계학회논문집A
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• 제23권6호
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• pp.979-987
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• 1999

In a high precision vertical machining center, the estimation of cutting forces is important for many reasons such as prediction of chatter vibration, surface roughness and so on, and cutting forces are difficult to predict because they are very complex and time variant. In order to predict the cutting forces of end-milling process for various cutting conditions, a mathematical model is important and this model is based on chip load, cutting geometry, and the relationship between cutting forces and chip loads. Specific cutting force coefficients of the model have been obtained as interpolation function types by averaging farces of cutting tests. In this paper, the coefficients are obtained by neural network and the results of the conventional method and those of the proposed method are compared. The results show that the neural network method gives more correct values than the function type and that in teaming stage as the omitted numbers of experimental data increases the average errors increase.

• 전기전자학회논문지
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• 제23권4호
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• pp.1203-1207
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• 2019

As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included in on-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitration result by combining multiple routers. Allocating desired bandwidths to the ports across the routers is more difficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed to overcome the limitations of existing local arbitration policies. Each IP can control the priority of a packet depending on the data communication requirement within the allocated bandwidth. The experimental results show that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple router on-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.

• 대한전자공학회논문지SD
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• 제45권12호
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• pp.8-14
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• 2008

본 논문에서는 $8{\times}8$ CNT 센서 어레이를 CMOS 공정 후 처리를 통하여 센서회로가 제작된 CMOS 칩에 집적시켜 측정장비 없이도 자체적으로 감지결과를 출력할 수 있는 센서 칩의 기본적인 플랫폼을 설계 제작한 결과를 보고한다. 센서 소자로는 알루미늄 패드 사이에 연결된 CNT network을 사용하였으며 생화학적 반응에 의하여 전기전도도가 변화하는 것을 감지한다. 표준 CMOS 공정의 감지회로는 CNT network의 저항 값 변동에 의해 ring oscillator의 주파수가 변동하는 것을 감지하는 방식을 사용한다. 제작된 CMOS 센서 칩을 활용하여 이를 대표적인 생화학물질인 glutamate을 검출하는데 실험적으로 적용하여 농도에 따른 출력결과 값을 얻는데 성공한다. 본 연구를 통하여 본 센서 칩 플랫폼을 이용한 상용화의 가능성을 확인하며, 추가적으로 개발이 필요한 기술에 대해 파악한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.83-87
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• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.

• 한국전산유체공학회지
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• 제14권4호
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• pp.86-92
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• 2009

Nowadays, the development of microfluidic chip [i.e. biochip, micro-total analysis system ($\mu$-TAS) and LOC (lab-on-a-chip)] becomes more active, and the microchannels to deliver fluid by pressure or electroosmotic forces tend to be more complex like electronic circuits or networks. For a simple network of channels, we may calculate the pressure and the flow rate easily by using suitable formula. However, for complex network it is not handy to obtain such information with that simple way. For this reason, Graphic User Interface (GUI) program which can rapidly give required information should be necessary for microchip designers. In this paper, we present a GUI program developed in our laboratory and the simple theoretical formula used in the program. We applied our program to simple case and could get results compared well with other numerical results. Further, we applied our program to several complex cases and obtained reasonable results.

• 한국전자파학회논문지
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• 제24권6호
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• pp.633-643
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• 2013

IC 내부의 전원분배망(PDN: Power Delivery Network) 회로를 분석하기 위해서는 IC의 디자인 정보가 담긴 파일이 필요하지만, 상용 IC(Commercial IC)의 경우 보안상의 이유로 디자인 정보를 제공하지 않고 있다. 하지만 온-칩 전원분배망(On-chip PDN) 특성이 포함된 경우에는 PCB와 패키지의 특성만으로는 정확한 해석이 어려우므로 본 연구에서는 IC 내부의 정보가 제공하지 않는 전원분배망(PDN) 회로의 추출에 관하여 연구를 하였다. IC 내부의 전원분배망(PDN)의 주파수에 대한 특성을 추출하기 위하여, IEC62014-3에서 제안하고 있는 추출용 보드를 제작하였고, 추출용 보드를 구성하고 있는 SMA 커넥터, 패드, 전송 선로, 그리고 QFN 패키지의 주파수에 대한 특성들을 분석하였다. 추출된 결과들은 디임베딩(de-embedding) 기술에 적용하여 IC 내부의 전원분배망(PDN) 회로를 S-parameter 기반으로 모델을 추출하였고, 평가용 보드의 전원분배망 결합회로(PDN Co-simulation)모델에 적용하여 측정과 비교한 결과, ~4 GHz까지 잘 일치하였다.