JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

Converting Interfaces on Application-specific Network-on-chip

  • Han, Kyuseung (SoC Design Research Group, Electronics and Telecommunications Research Institute (ETRI)) ;
  • Lee, Jae-Jin (SoC Design Research Group, Electronics and Telecommunications Research Institute (ETRI)) ;
  • Lee, Woojoo (Department of Electronic Engineering, Myongji University)
  • Received : 2017.01.17
  • Accepted : 2017.07.05
  • Published : 2017.08.30
Download PDF
⟨ Previous Next ⟩

Abstract

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.

Keywords

References

  1. S. Murali et al., "Designing Application-specific Networks on Chips with Floorplan Information," in Proc. of the Int'l Conf. on Computer-Aided Design, pp. 355-362, 2006.
  2. M. Dall'Osso et al., "Xpipes: A latency insensitive parameter- ized network-on-chip architecture for multi-processor SoCs," in Proc. of the IEEE Int'l Conf. on Computer Design, pp. 45-48, 2012.
  3. D. Zhu et al., "TAPP: Temperature-aware pplication mapping for NoC-based many-core processors," in Proc. of the Int'l Conf.. on Design, Automation & Test in Europe, pp. 1241-1244, 2015.
  4. W. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2003.
  5. P. P. Pande et al., "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Trans. Comput., vol. 54, pp. 1025-1040, Aug 2005. https://doi.org/10.1109/TC.2005.134
  6. U. Y. Ogras, J. Hu and R. Marculescu, "Key research problems in NoC design: A holistic perspective," in Proc. of the Int'l Conf. on Hardware/Software Codesign and System Synthesis, pp. 69-74, 2005.
  7. A. B. Kahng et al., "ORION 2.0: A fast and accurate noc power and area model for early-stage design space exploration," in Proceedings of the Int'l Conference on Design, Automation & Test in Europe, pp. 423-428, 2009.
  8. J. Hu and R. Marculescu, "Energy- and performance-aware mapping for regular noc architectures," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 551-562, 2005. https://doi.org/10.1109/TCAD.2005.844106
  9. M. Palesi et al., "A methodology for design of application specific deadlock-free routing algorithms for noc systems," in Pro- ceedings of the Int'l Conf. on Hardware/Software Codesign and System Synthesis, pp. 142-147, 2006.
  10. K. Han, J. J. Lee, J. Lee, W. Lee, and M. Pedram, "TEI-NoC: Optimizing Ultra-Low Power NoCs Exploiting the Temperature Effect Inversion," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2017.2693269
  11. K. Goossens et al., "A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SoC Design and Verification," in Proc. of the Interna- tional Conference on Design, Automation & Test in Europe, pp. 1182-1187, 2005.
  12. L. Benini, "Application Specific NoC Design," in Proc. of the Int'l Conf. on Design, Automation & Test in Europe, pp. 1-5, 2006.
  13. S. Kwon, S. Pasricha and J. Cho, "POSEIDON: A framework for application-specific network-on-chip synthesis for heterogeneous chip multiprocessors," in Proc. of the Int'l Symp. on Quality Electronic Design, pp. 1-7, 2011.
  14. K. S. M. Li, "CusNoC: Fast full-chip custom NoC generation," IEEE Transactions on Very Large Scale Integr. Sys., vol. 21, pp. 692-705, April 2013. https://doi.org/10.1109/TVLSI.2012.2195688
  15. J. Soumya and S. Chattopadhyay, "Application-specific network-on-chip synthesis with flexible router placement," J. Syst. Archit., vol. 59, pp. 361-371, Aug 2013. https://doi.org/10.1016/j.sysarc.2013.05.013
  16. B. Grot et al., "Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees," in Proceed- ings of the Int'l Symp. on Comp. Arch., pp. 401-412, 2011.
  17. A. K. Mishra, O. Mutlu and C. R. Das, "A heterogeneous mul- tiple network-on-chip design: An application-aware approach," in Proc. of the Design Automation Conf., pp. 36:1-36:10, 2013.
  18. Arteris, "http://www.arteris.com/flexnoc."
  19. ARM, "http://www.arm.com/products/system-ip/interconnect/corelink-nic-family.php."
  20. Sonics, "http://sonicsinc.com."
  21. A. Radulescu et al., "An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration," in Proc. of the Int'l Conf. on Design, Auto. & Test, vol. 2, pp. 878-883, 2004.
  22. K. Goossens, J. Dielissen and A. Radulescu, "Aethereal network on chip: concepts, architectures, and implementations," IEEE Design & Test of Computers, vol. 22, pp. 414-421, Sept 2005. https://doi.org/10.1109/MDT.2005.99
  23. J. Sparsø, E. Kasapaki and M. Schoeberl, "An area-efficient net- work interface for a tdm-based network-on-chip," in Proceed- ings of the Int'l Conf. on Design, Auto. & Test in Europe, pp. 1044-1047, 2013.
  24. A. Radulescu et al., "An efficient on-chip ni offering guaran- teed services, shared-memory abstraction, and flexible network configuration," IEEE Trans. on Computer-Aided Design of Integr. Circuits and Systems, vol. 24, pp. 4-17, Jan 2005. https://doi.org/10.1109/TCAD.2004.839493
  25. X. Yang et al., "Nisar: An axi compliant on-chip ni architecture offering transaction reordering processing," in Proc. of the Int'l Conf. on ASIC, pp. 890-893, 2007.
  26. T. Bjerregaard et al., "An ocp compliant network adapter for gals-based soc design using the mango network-on-chip," in Proceedings of the Int'l Symp. on System-on- Chip, pp. 171-174, 2005.
  27. ARM,"https://www.arm.com/products/system-ip/amba-specifications."
  28. Wishbone, "https://opencores.org/opencores,wishbone."
  29. TileLink,"http://bar.eecs.berkeley.edu/projects/2014-tilelink.html."
  30. XILINX, "https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html."