• Journal of the Institute of Convergence Signal Processing
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• v.7 no.3
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• pp.87-94
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• 2006

For realizing an ubiquitous home network(uHome-net), various sensors should be able to be connected to an integrated wire/wireless sensor network. This paper describes an application case of applying LonWorks technology being widely used in control network to wire/wireless sensor network in uHome-net and the design and application of LonRF device that consists of a neuron chip including LonTalk protocol, a 433.92MHz RF transceiver, a sensor, and application programs. As an application example of the LonRF device, the LonRF smart badge that can measure the 3D location of objects in indoor environment and interwork with the uHome-net was developed. LonRF device based home network services were realized on the uHome-net testbed such as indoor positioning service, remote surveillance service and remote metering service were realized. This research shows that LonWorks technology based sensor network could be applicable to the control network in an ubiquitous home network and the LonRF device can be used as a wireless node in various sensor networks.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.103-110
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• 2014

Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Journal of the Korean Institute of Intelligent Systems
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• v.21 no.5
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• pp.595-601
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• 2011

This paper presents balancing control of inverted pendulum on the ROBOKER arm using visual information. The angle of the inverted pendulum placed on the robot arm is detected by a stereo camera and the detected angle is used as a feedback and tracking error for the controller. Thus, the overall closed loop forms a visual servoing control task. To improve control performance, neural network is introduced to compensate for uncertainties. The learning algorithm of radial basis function(RBF) network is performed by the digital signal controller which is designed to calculate floating format data and embedded on a field programmable gate array(FPGA) chip. Experimental studies are conducted to confirm the performance of the overall system implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.57-64
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• 2006

Multiprocessor system on chip (MPSoC) platforms has set a new innovative trend for the SoC design. Quality of service parameters and performance matrix are leading to the adoption of new design methodology for SoC, which will incorporate highly scalable, reusable, predictable, cost and energy efficient platform not only for underlying communication backbone but also for the entire system architecture of NOC. Like the layered architecture for the communication backbone of NOC, we have proposed the entire system architecture for NOC to be a seven layered architecture in itself. Such a platform can separate the domain specific issues which will model concurrency along with the synchronization issues more effectively. For such a layered architecture, model of computation will provide a framework to that can model concurrency and synchronization issues which are natural for any application. Therefore it becomes extremely important to use a right computation model in a specific NOC region.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.74-82
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• 2015

As the complexity of an electronic device and the reduction of its operating voltage is progressing, susceptibility test of the chip and module for internal or external noises is essential. Although the immunity compliance of the chip was served with IEC 62132-4 Direct Power Injection method as an industry standard, in fact, EM immunity of the chip is influenced by their Power Domain Network (PDN). This paper evaluates the EM noise tolerance of a PLL and compares their noise transfer characteristics to the PLL on various PCB boards. To make differences of the PDNs of PCBs, various PCBs with or without LDO and with several types of capacitors are tested. For evaluation of discrepancies between EM characteristics of an IC only and the IC on real boards, the analysis of the noise transfer characteristics according to the PDNs shows that it gives important information for the design having robust EM characteristics. DPI measurement results show that greatly improved immunity of the PLL in the low-frequency region according to using the LDO and a frequency change of the PLL according to the DPI could also check with TEM cell measurement spectrum.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.10
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• pp.871-880
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• 2000

A twin-servo mechanism is used to increase the payload capacity and assembling speed of high precision motion control systems such as semiconductor chip mounters. In this paper, we focus on the modeling of the twin-servo system and propose its network representation. And also, we propose a robust synchronizing motion control algorithm to cancel out the skew motion of the twin-servo system caused by different dynamic characteristics of two driving systems and the vibration generated by high accelerating and decelerating motions. The proposed control algorithm consists of separate feedback motion control algorithms for each driving system and a skew motion compensation algorithm. A robust tracking controller based on internal-loop compensation is proposed as a separate motion controller and its disturbance attenuation property is shown. The skew motion compensation algorithm is also designed to maintain the synchronizing motion during high speed operation, and the stability of the whole closed loop system is proved based on passivity theory. Finally, experimental results are shown to illustrate control performance.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.254-257
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• 1993

This paper presents a new method to implement Hebbian learning method on artificial neural network. In hebbian learning algorithm, complexity in terms of multiplications is high. To save the chip area, we consider a new learning circuit. By calculating similarity, or correlation between $X_i$ and $O_i$, large portion of circuits commonly used in conventional neural networks is not necessary for this new hebbian learning circuit named COR. The output signals of COR is applied to weight storage capacitors for direct control the voltages of the capacitors. The weighted sum, ${\Sigma}W_{ij}O_j$, is realized by multipliers, whose output currents are summed up in one line which goes to learning circuit or output circuit. The drain current of the multiplier can produce positive or negative synaptic weights. The pass transistor selects eight learning mode or recall mode. The layout of an learnable six-neuron fully connected Hopfield neural network is designed, and is simulated using PSPICE. The network memorizes, and retrieves the patterns correctly under the existence of minor noises.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.1
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• pp.115-121
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• 2004

In this paper, a new distributed intelligent control module based on LonWoks fieldbus for air handling unit(AHU) of heating, ventilating and air-conditioning(HVAC) is proposed to replace with a conventional direct digital control(DDC) system with 32 bit microprocessor. The proposed control architecture has a excellent features such as highly compact and flexible function design, a low priced smart front-end and reliable performance with various functions. This also addresses issues in control network configuration, logical design of field devices by S/W tool, Internet networking and electronic element installation. Experimental results for showing the system performance are also included in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.98-101
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• 2007

A fully integrated 5-GHz CMOS power amplifier for IEEE 802.11a WLAN applications is implemented using $0.18-{\mu}m$ CMOS technology. An on-chip transmission-line transformer is used for output matching network and voltage combining. Input balun, inter-stage matching components, output transmission line transformer and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier occupies a total area of $1.7mm{\times}1.2mm$. At a 3.3-V supply voltage, the amplifier exhibits a 22.6-dBm output 1-dB compression point, 23.8-dBm saturated output power, 25-dB power gain. The measured power added efficiency (PAE) is 20.1 % at max. peak, 18.8% at P1dB. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12dBm of average power at the EVM of -25dB.