• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• ETRI Journal
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• v.29 no.3
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• pp.371-380
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• 2007

This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 ${\mu}m$ SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.

• ETRI Journal
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• v.29 no.1
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• pp.59-69
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• 2007

We designed and fabricated a vision chip for edge detection with a $160{\times}120$ pixel array by using 0.35 ${\mu}m$ standard complementary metal-oxide-semiconductor (CMOS) technology. The designed vision chip is based on a retinal structure with a resistive network to improve the speed of operation. To improve the quality of final edge images, we applied a saturating resistive circuit to the resistive network. The light-adaptation mechanism of the edge detection circuit was quantitatively analyzed using a simple model of the saturating resistive element. To verify improvement, we compared the simulation results of the proposed circuit to the results of previous circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.171-174
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• 2003

In this paper, a Learning module for a reconfigurable neural network processor(ERNIE) was proposed for an On-chip learning. The existing reconfigurable neural network processor(ERNIE) has a much better performance than the software program but it doesn't support On-chip learning function. A learning module which is based on Back Propagation algorithm was designed for a help of this weak point. A pipeline structure let the learning module be able to update the weights rapidly and continuously. It was tested with five types of alphabet font to evaluate learning module. It compared with C programed neural network model on PC in calculation speed and correctness of recognition. As a result of this experiment, it can be found that the neural network processor(ERNIE) with learning module decrease the neural network training time efficiently at the same recognition rate compared with software computing based neural network model. This On-chip learning module showed that the reconfigurable neural network processor(ERNIE) could be a evolvable neural network processor which can fine the optimal configuration of network by itself.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.108-116
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• 2013

The input buffer in Network on Chip (NoC) router plays a key role in on-chip-network performance, which is utilized in flow control and virtual channel. However, increase in area and power due to input buffers as the network size gets larger is becoming severe. To solve this problem, a bufferless deflection routing without input buffer was suggested. Since the bufferless deflection routing shows poor performance at high network load, other approaches which combine the deflection routing with small size side buffers were also proposed. Nonetheless these new methods still show deficiencies caused by frequent path collisions. In this paper, we propose a modified deflection routing technique using a location based priority. In comparison with existing deflection routers, experimental results show improvement by 12% in throughput with only 3% increase in area.

• Journal of the Korean Society for Precision Engineering
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• v.12 no.8
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• pp.53-62
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• 1995

In recent years, the rapid development of the machine tool and tough insert has made metal removal rates increase, and automatic system without human supervision requires a higher degree reliability of machining process. Therefore the control of chips is one of the important topics which deserves much attention. The chip classification was made based upon standard deviation of the mean cutting force measured by a tool dynamometer. STS304was chosen as the workpiece which is known as the difficult-to-cut material and mainly saw-toothed chip produced, and the chip type according to the standard deviation of mean cutting force was classified into five categories in this experiment. Long continuous type chip which interrupts the normal cutting process, and damages the operator, tool and workpiece has low standard deviation value, while short broken type chip, which is favourable chip for disposal, has relatively large standard deviation value. In addition, we investigated the possibility that the chip type can be predicted analyzing the relationship between chip type and cutting condition by the trained neural network, and obtained favourable results by which the chip type can be predicted with cutting conditon before cutting process.