• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.284-284
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• 2011

Recently, the increasing degree of device integration in the fabrication of Si semiconductor devices, etching processes of nano-scale materials and high aspect-ratio (HAR) structures become more important. Due to this reason, etch selectivity control during etching of HAR contact holes and trenches is very important. In this study, The etch selectivity and etch rate of TEOS oxide layer using ACL (amorphous carbon layer) mask are investigated various process parameters in CH2F2/C4F8/O2/Ar plasma during etching TEOS oxide layer using ArF/BARC/SiOx/ACL multilevel resist (MLR) structures. The deformation and etch characteristics of TEOS oxide layer using ACL hard mask was investigated in a dual-frequency superimposed capacitively coupled plasma (DFS-CCP) etcher by different fHF/ fLF combinations by varying the CH2F2/ C4F8 gas flow ratio plasmas. The etch characteristics were measured by on scanning electron microscopy (SEM) And X-ray photoelectron spectroscopy (XPS) analyses and Fourier transform infrared spectroscopy (FT-IR). A process window for very high selective etching of TEOS oxide using ACL mask could be determined by controlling the process parameters and in turn degree of polymerization. Mechanisms for high etch selectivity will discussed in detail.

• KSBB Journal
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• v.28 no.4
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• pp.254-259
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• 2013

Herein we present a diagnostic paper chip that can quantitatively detect albumin without external electronic reader and dispensing apparatus. We fabricated a diagnostic paper chip device by printing wax barrier on the paper and wicking it with citrate buffer and tetrabromophenol blue to detect albumin in sample solution. The paper chip is so simple that we dropped a sample solution at sample pad and measure the ratio of two travel distances of the sample solvent and albumin under the name of retention factor. Our result confirmed that the retention factor was constant in the samples with same concentration of albumin and useful determinant for the measurement of albumin concentration. The paper chip is affordable and equipment-free, and close to ideal point-of-care test in accordance with the assured criteria, outlined by the World Health Organization. We assume that this diagnostic paper chip will expand the concept of colorimetric determination and provide a inexpensive diagnostic method to aging society and developing country.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.693-695
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• 2012

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET as the device to be able to use until nano scale has the adventage to reduce the short channel effects. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change od the breakdown voltage for gate oxide thickness and channel thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.52-52
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• 2009

To date, chalcogenide alloy such as $Ge_2Sb_2Te_5$(GST) have not only been rigorously studied for use in Phase Change Random Access Memory(PRAM) applications, but also temperature gap to make different states is not enough to apply to device between amorphous and crystalline state. In this study, we have investigated a new system of phase change media based on the In-Sb-Te(IST) ternary alloys for PRAM. IST chalcogenide thin films were prepared in trench structure (aspect ratio 5:1 of length=500nm, width=100nm) using Tri methyl Indium $(In(CH_3)_4$), $Sb(iPr)_3$ $(Sb(C_3H_7)_3)$ and $Te(iPr)_2(Te(C_3H_7)_2)$ precursors. MOCVD process is very powerful system to deposit in ultra integrated device like 100nm scaled trench structure. And IST materials for PRAM can be grown at low deposition temperature below $200^{\circ}C$ in comparison with GST materials. Although Melting temperature of 1ST materials was $\sim 630^{\circ}C$ like GST, Crystalline temperature of them was ~$290^{\circ}C$; one of GST were $130^{\circ}C$. In-Sb-Te materials will be good candidate materials for PRAM applications. And MOCVD system is powerful for applying ultra scale integration cell.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.157-157
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• 2008

As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.881-883
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• 2005

In case is below length 100nm of gate, various kinds problem can be happened with by threshold voltage change of device, occurrence of leakage current by tunneling because thickness of oxide by 1.5nm low scaling is done and doping concentration is increased. SiO$_2$ dielectric substance can not be used for gate insulator because is expected that tunneling current become 1A/cm$^2$ in 1.5nm thickness low. In this paper, devised double gate MOSFET(DGMOSFET) to decrease effect of leakage current by this tunneling. Therefore, could decrease effect of these leakage current in thickness 1nm low of SiO$_2$ dielectric substance. But, very big gate insulator of permittivity should be developed for develop device of nano scale.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

• Advances in nano research
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• v.13 no.3
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• pp.259-267
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• 2022

Two-dimensional (2D) transition metal carbides/nitrides or "MXenes" belong to a diverse-class of layered compounds, which offer composition- and electric-field-tunable electrical and physical properties. Although the majority of the MXenes, including Ti₃C₂T_x, are metallic, they typically show semiconductor-like behaviour in their percolated thin-film structure; this is also the most common structure used for fundamental studies and prototype device development of MXene. Magnetoconductance studies of thin-film MXenes are central to understanding their electronic transport properties and charge carrier dynamics, and also to evaluate their potential for spin-tronics and magnetoelectronics. Since MXenes are produced through solution processing, it is desirable to develop deposition strategies such as inkjet-printing to enable scale-up production with intricate structures/networks. Here, we systematically investigate the extrinsic negative magnetoconductance of inkjetprinted Ti₃C₂T_x MXene thin-films and report a crossover from weak anti-localization (WAL) to weak localization (WL) near 2.5K. The crossover from WAL to WL is consistent with strong, extrinsic, spin-orbit coupling, a key property for active control of spin currents in spin-orbitronic devices. From WAL/WL magnetoconductance analysis, we estimate that the printed MXene thin-film has a spin orbit coupling field of up to 0.84 T at 1.9 K. Our results and analyses offer a deeper understanding into microscopic charge carrier transport in Ti₃C₂T_x, revealing promising properties for printed, flexible, electronic and spinorbitronic device applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.25-31
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• 2004

In this paper, we introduce kinetic Monte Carlo (kMC) methods for simulating diffusion process in nano-scale device fabrication. At first, we review kMC theory and backgrounds and give a simple point defect diffusion process modeling in thermal annealing after ion (electron) implantation into Si crystalline substrate to help understand kinetic Monte Carlo methods. kMC is a kind of Monte Carlo but can simulate time evolution of diffusion process through Poisson probabilistic process. In kMC diffusion process, instead of. solving differential reaction-diffusion equations via conventional finite difference or element methods, it is based on a series of chemical reaction (between atoms and/or defects) or diffusion events according to event rates of all possible events. Every event has its own event rate and time evolution of semiconductor diffusion process is directly simulated. Those event rates can be derived either directly from molecular dynamics (MD) or first-principles (ab-initio) calculations, or from experimental data.