• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.120-121
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• 2007

Nano-floating gate memory (NFGM) devices were fabricated by using the low temperature poly-Si thin films crystallized by ELA and the $In_2O_3$ nano-particles embedded in polyimide layers as charge storage. Memory effect due to the charging effects of $In_2O_3$ nano-particles in polyimide layer was observed from the TFT NFGM. The post-annealing in 3% diluted hydrogen $(H_2/N_2)$ ambient improved the retention characteristics of $In_2O_3$ nano-particles embedded poly-Si TFT NFGM by reducing the interfacial states as well as grain boundary trapping states.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1226-1227
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• 2008

In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.67-68
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• 2006

Floating gate non-volatile memory devices with Au nano-particles embedded in SiON or $SiO_2$ dielectrics were fabricated by digital sputtering method. The size and the density of Au are 4nm and $2{\times}10^{-12}cm^{-2}$, respectively. The floating gate memory of MOSFET with 5nm tunnel oxide and 45nm control oxide have been fabricated. This devices revealed a memory effect which due to proGrainming and erasing works perform by a gate bias stress repeatedly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.647-648
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• 2006

This paper presents the design results of peripheral circuits of non-volatile memory of nano floating gate cells. The designed peripheral circuits included command decoder, decoders, sense amplifiers and oscillator, which are targeted with 0.35um technology EEPROM process for operating test and reliable test. The simulation results show each operation and test mode of output voltage for word line, bit line, well and operating of sense amplifier.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.307.2-307.2
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• 2016

In this study, we synthesized Au nanoparticles (AuNPs) in polyacrylonitrile (PAN) thin films using a simple annealing process in the solid phase. The synthetic conditions were systematically controlled and optimized by varying the concentration of the Au salt solution and the annealing temperature. X-ray photoelectron spectroscopy (XPS) confirmed their chemical state, and transmission electron microscopy (TEM) verified the successful synthesis, size, and density of AuNPs. Au nanoparticles were generated from the thermal decomposition of the Au salt and stabilized during the cyclization of the PAN matrix. For actual device applications, previous synthetic techniques have required the synthesis of AuNPs in a liquid phase and an additional process to form the thin film layer, such as spin-coating, dip-coating, Langmuir-Blodgett, or high vacuum deposition. In contrast, our one-step synthesis could produce gold nanoparticles from the Au salt contained in a solid matrix with an easy heat treatment. The PAN:AuNPs composite was used as the charge trap layer of an organic nano-floating gate memory (ONFGM). The memory devices exhibited a high on/off ratio (over $10^6$), large hysteresis windows (76.7 V), and a stable endurance performance (>3000 cycles), indicating that our stabilized PAN:AuNPs composite film is a potential charge trap medium for next generation organic nano-floating gate memory transistors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.21-26
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• 2008

We fabricated nano-particles of ZnO, $In_2O_3$ and $SnO_2$ by using the chemical reaction between metal thin films and polyamic acid. The average size and density of these ZnO, $In_2O_3$ and $SnO_2$ nano-particles was approximately 10, 7, and 15 nm, and $2{\times}10^{11},\;6{\times}10^{11},\;2.4{\times}10^{11}cm^{-2}$, respectively. Then, we fabricated nano-floating gate memory (NFGM) devices with ZnO and $In_2O_3$ nano-particles embedded in the devices' polyimide dielectrics and silicon dioxide layers as control and tunnel oxides, respectively. We measured the current-voltage characteristics, endurance properties and retention times of the memory devices using a semiconductor parameter analyzer. In the $In_2O_3$ NFGM, the threshold voltage shift (${\Delta}V_T$) was approximately 5 V at the initial state of programming and erasing operations. However, the memory window rapidly decreased after 1000 s from 5 to 1.5 V. The ${\Delta}V_T$ of the NFGM containing ZnO was approximately 2 V at the initial state, but the memory window decreased after 1000 s from 2 to 0.4 V. These results mean that metal-oxide nano-particles have feasibility to apply NFGM devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.18-26
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• 2004

Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.325-327
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• 2011

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a $SiO_2/Si$ substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.