• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.10
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• pp.510-514
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• 2004

In this paper, we analytically examine the voltage transfer function dependent on input conditions for an N-Input NAND Gate. The logic threshold voltage, defined as a voltage at which the input and the output voltage become equal, changes as the input condition changes for a static NAND Gate. The logic threshold voltage has the highest value when all the N-inputs undergo transitions and it has the lowest value when only the last input connected to the last NMOS to ground, makes a transition. This logic threshold voltage difference increases as the number of inputs increases. Therefore, in order to provide a near symmetric voltage transfer function, a multistage N-Input Gate consisting of 2-Input Logic Gates is desirable over a conventional N-Input Gate.

• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.650-656
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• 2016

Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors and CMOS inverter are reported. Three, five and seven stages ring VCO circuits are designed. Coarse and fine tuning have been done using two different supply sources. The frequency with coarse tuning varies from 3.31 GHz to 5.60 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages VCO respectively. Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. Results of power consumption and phase noise for the VCO circuits are also been reported. Results of proposed VCO circuits have been compared with previously reported circuits and present circuit approach show significant improvement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.260-264
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• 2017

Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.1-6
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• 2011

Low-power logic gates, i.e. inverter, NAND, and NOR, are proposed employing only n-channel oxide thin film transistors (TFTs). The proposed circuits were designed to prevent the pull-up and pull-down switches from being turned on simultaneously by using asymmetric feed-through and bootstrapping, thereby exhibited same output voltage swing as the input signal and no static current. The inverter is composed of 5 TFTs and 2 capacitors. The NAND and the NOR gates consist of 10 TFTs and 4 capacitors respectively. The operations of the logic gates were confirmed successfully by SPICE simulation using oxide TFT model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.263-268
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• 2003

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1611-1614
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• 2010

The explosion of a nuclear weapon radiates a gamma-ray in the form of a transient pulse. If the gamma-ray introduces to semiconductor devices, much Electron-Hole Pairs(EHPs) are generated in depletion region of the devices[7]. as a consequence of that, high photocurrent is created and causes upset, latchup and burnout of semiconductor devices[8]. This phenomenon is known for Transient Radiation Effects on Electronics(TREE), also called dose-rate effects. In this paper 3D structure of inverter and NAND gate device was designed and transient pulse gamma-ray was modeled. So simulation for transient radiation effect on inverter and NAND gate was accomplished and mechanism for upset and latchup was analyzed.