JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

  • Baek, Myung-Hyun (Electrical and Computer Engineering, Seoul National University) ;
  • Kim, Do-Bin (Electrical and Computer Engineering, Seoul National University) ;
  • Kim, Seunghyun (Electrical and Computer Engineering, Seoul National University) ;
  • Lee, Sang-Ho (Electrical and Computer Engineering, Seoul National University) ;
  • Park, Byung-Gook (Electrical and Computer Engineering, Seoul National University)
  • Received : 2016.08.25
  • Accepted : 2016.11.24
  • Published : 2017.04.30
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Abstract

Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

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References

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