Journal of Applied Reliability (한국신뢰성학회지:신뢰성응용연구)

The Korean Reliability Society (한국신뢰성학회)
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Nanoscale NAND SONOS memory devices including a Seperated double-gate FinFET structure

  • Kim, Hyun-Joo (Dept. of Information Display, Hanyang University) ;
  • Kim, Kyeong-Rok (Dept. of Nanoscale Semiconductor Engineering, Hanyang University) ;
  • Kwack, Kae-Dal (Dept. of Information Display, Hanyang University)
  • Received : 2009.11.19
  • Accepted : 2010.01.08
  • Published : 2010.03.25
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Abstract

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

Keywords

References

  1. F. Hofmann et al(2005), "NVM based on FinFET device structures" Solid-State Electron. 49, 1799. https://doi.org/10.1016/j.sse.2005.10.012
  2. N. Gupta(2007), "Threshold voltage modeling and gate oxide thickness effect on polycrystalline silicon thin-film transistors" Physica Scripta 76, 628. https://doi.org/10.1088/0031-8949/76/6/006
  3. B. G. Park et al(2006), "Novel Device Structures for Charge Trap Flash Memories" IEEE Solid-State and Integrated Circuit Technology, ICSICT '06.
  4. K. H. Kim and H. J. Lee(2006), "Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate" IEICE Trans. Electron. E89-C, 578. https://doi.org/10.1093/ietele/e89-c.5.578
  5. J. Lee et al(2002), "High-Performance 1-Gb NAND Flash Memory With 0.12-${\mu}m$ Technology" IEEE J. Solid-St. Circ. 37, 1502. https://doi.org/10.1109/JSSC.2002.802352
  6. T. Tanaka et al(1994), "A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory" J. Solid-St. Circ. 29, 1366. https://doi.org/10.1109/4.328638
  7. K. Takeuchi et al(1998), "A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories" J. Solid-St. Circ. 33, 1228. https://doi.org/10.1109/4.705361
  8. J. Lee et al(2003), "A 90-nm CMOS 1.8-V 2-Gb NAND Flash Memory for Mass Storage Applications" J. Solid-St Circ. 38, 1934. https://doi.org/10.1109/JSSC.2003.818143
  9. S. K. Sung et al(2006), "Fully Integrated SONOS Flash Memory Cell Array With BT (Body Tied)-FinFET Structure" IEEE Trans. Nanotechnol. 5, 174. https://doi.org/10.1109/TNANO.2006.869954
  10. Y. K. Lee et al(2004), "Twin SONOS Memory With 30-nm Storage Nodes Under a Merged Gate Fabricated With Inverted Sidewall and Damascene Process" IEEE Electr. Device Lett. 25, 317. https://doi.org/10.1109/LED.2004.826535
  11. H. G. Kim et al(2007), "Device optimization of the FinFET having an isolated n+/p+ strapped gate" Microelectron. Eng. 84, 1656 (2007). https://doi.org/10.1016/j.mee.2007.01.160
  12. Y. Liu et al(2004), "A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel" IEEE Electr. Device Lett. 25, 510. https://doi.org/10.1109/LED.2004.831205
  13. M. Ieong et al(2002), " High Performance Double-Gate Device Technology Challenges and Opportunities" IEEE Computer Society, ISQED'02.
  14. S. J. Cho et al(2006), "Design and Optimization of Two-Bit Double-Gate Nonvolatile Memory Cell for Highly Reliable Operation" IEEE Trans. Nanotechnol. 5, 180. https://doi.org/10.1109/TNANO.2006.869943