• ETRI Journal
• /
• v.9 no.1
• /
• pp.118-124
• /
• 1987

Short channel n-MOSFET의 드레인-소오스 사이의 breakdown은 단순한 접합 breakdown이 아닌 avalanche-induced breakdown으로 p-MOSFET, long channel n-MOSFET의 breakdown 전압보다 훨씬 작은 값을 갖는다. Short channel n-MOSFET의 breakdown의 특징은 current-controlled 부저항 특성(snapback)이 나타나고, 게이트 전압에 따라 breakdown 전압보다 작은 sustainning 전압이 존재한다. 이와 같은 sustainning 전압은 short channel n-MOSFET의 안정한 동작에 또 하나의 제한 요소가 될 수 있다. 따라서 공정 및 회로 시뮬레이션을 위해, short channel n-MOSFET의 avalanche breakdown 현상에 대한 정확한 분석이 요구된다. Short channel n -MOSFET의 avalanche breakdown 현상을 분석하기 위해서Parasitic bipolar transistor를 도입한 분석적 모델을 이용하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.7
• /
• pp.464-472
• /
• 2001

Asymmetric n-MOSFET＇s for improving packing density have been fabricated with 0.35 ${\mu}{\textrm}{m}$ CMOS process. Electrical characteristics of asymmetric n-MOSFET show a lower saturation drain current and a higher linear resistance compared to those of symmetric devices. Substrate current of asymmetric MOSFET is lower than that of symmetric devices. Asymmetric n-MOSFET＇s have been modeled using a parasitic resistance associated with abnormally structured drain or source and a conventional n-MOSFET model. MEDICI simulation has been done for accuracy of this modeling. Simulated values of reverse as we11 as forward saturation drain current show good agreement with measured values for asymmetric device.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.4
• /
• pp.180-186
• /
• 2023

Positive bias temperature instability (PBTI) degradation of n⁺ and p⁺ poly-Si gate high-voltage(HV) SiO2 dielectric nMOSFETs was investigated. Unlike the expectation that degradation of n⁺/nMOSFET will be greater than p⁺/nMOSFET owing to the oxide electric field caused by the gate material difference, the magnitude of the PBTI degradation was greater for the p⁺/nMOSFET than for the n⁺/nMOSFET. To analyze the cause, the interface state and oxide charge were extracted for each case, respectively. Also, the carrier injection and trapping mechanism were analyzed using the carrier separation method. As a result, it has been verified that hole injection and trapping by the p⁺ poly-Si gate accelerates the degradation of p⁺/nMOSFET. The carrier injection and trapping processes of the n⁺ and p⁺ poly-Si gate high-voltage nMOSFETs in PBTI are detailed in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.9 s.339
• /
• pp.9-18
• /
• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.11
• /
• pp.62-69
• /
• 1998

The general degradation model has been applied to analyze the hot carrier induced degradation of the DC and RF characteristics of RF-nMOSFET. The degradation of cut-off frequency has been severer than the degradation of bulk MOSFET drain current. The value of the degradation rate n and the degradation parameter m for RF-nMOSFET has been equal to those for bulk MOSFET. The decrease of device degradation with the increase of fingers could be explained by the large source/drain parasitic resistance and drain saturation voltage. It has been also found that the RF performance degradation could be explained by the decrease of $g_{m}$ and $C_{gd}$ and the increase of $g_{ds}$ after stress. The degradation of the DC and RF characteristics of RF-nMOSFET could be predicted by the measurement of the substrate current.t.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.775-777
• /
• 2016

In this paper presents an analysis of pulsed radiation effects of unit devices. Unit devices are the nMOSFET, pMOSFET, NPN Transistor and those fabricated by the 0.18um CMOS process. Pulsed radiation test results in nMOSFET, the photocurrent of tens nA was generated in $2.07{\times}10^8rad(si)/s$. For the pMOSFET, a photocurrent generation was not observed in $3{\times}10^8rad(si)/s$. For the NPN transistor, the photocurrent was generated with about 1uA. Therefore, the MOSFET must be used than BJT transistor when radhard IC design.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.10
• /
• pp.1927-1934
• /
• 2016

In this paper, we proposed a I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistor) structure in order to mitigate a radiation-induced leakage current path in an isolation oxide interface of a silicon-based standard n-MOSFET. The proposed I-gate n-MOSFET structure was designed by using a layout modification technology in the standard 0.18um CMOS (Complementary Metal Oxide Semiconductor) process, this structure supplements the structural drawbacks of conventional radiation-tolerant electronic device using layout modification technology such as an ELT (Enclosed Layout Transistor) and a DGA (Dummy Gate-Assisted) n-MOSFET. Thus, in comparison with the conventional structures, it can ensure expandability of a circuit design in a semiconductor-chip fabrication. Also for verification of a radiation-tolerant characteristic, we carried out M&S (Modeling and Simulation) using TCAD 3D (Technology Computer Aided Design 3-dimension) tool. As a results, we had confirmed the radiation-tolerant characteristic of the I-gate n-MOSFET structure.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.4
• /
• pp.21-27
• /
• 2009

In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.34D no.8
• /
• pp.35-40
• /
• 1997

To suppress the short channel effects in nMOSFET with 0.1.mu.m channel length, we have fabricated and characterized the ISRC n MOSFET with several process condition. When the recess oxide thickness is 100nm and the channel dose for threshold voltge adjustment is 6*10$^{12}$ /c $m^{-2}$ , B $F_{2}$$^{+}$, the maximum transconductance at $V_{DS}$ =2.0V is 455mS/mm and the BIDL is kept within 67mV. By comparing the ISRC n MOSFET with the conventioanl SHDD (shallowly heavily dopped drain) nMOSFET, we verify the suppression of short channel effects ISRC structure.e.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.10
• /
• pp.1-7
• /
• 2004

In order to enhance the electron mobility in SOI n-MOSFET, we fabricated fully depletion(FD) n-MOSFET on the strained Si/relaxed SiGa/SiO$_2$/Si structure(strained Si/SGOI) formed by inserting SiGe layer between a buried oxide(BOX) layer and a top silicon layer. The summated thickness of the strained Si and relaxed SiGe was fixed by 12.8 nm and then the dependency of electron mobility on strained Si thickness was investigated. The electron mobility in the FD n-MOSFET fabricated on the strained Si/SGOI enhanced about 30-80% compared to the FD n-MOSFET fabricated on conventional SOI. However, the electron mobility decreased with the strained Si thickness although the inter-valley phonon scattering was reduced via the enhancement of the Ge mole fraction. This result is attributed to the increment of intra-valley phonon scattering in the n-channel 2-fold valley via the further electron confinement as the strained Si thickness was reduced.