Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Electric Characteristics and Modeling of Asymmetric n-MOSFETs for Improving Packing Density

집적도 향상을 위한 비대칭 n-MOSFET의 전기적 특성 및 모델링

  • 공동욱 (텔레포스(주) 연구개발부) ;
  • 이재성 (위덕대학교 정보통신공학과) ;
  • 남기홍 (경일대학교 전자정보공학과) ;
  • 이용현 (경북대학교 전자전기공학부)
  • Published : 2001.07.01
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Abstract

Asymmetric n-MOSFET＇s for improving packing density have been fabricated with 0.35 ${\mu}{\textrm}{m}$ CMOS process. Electrical characteristics of asymmetric n-MOSFET show a lower saturation drain current and a higher linear resistance compared to those of symmetric devices. Substrate current of asymmetric MOSFET is lower than that of symmetric devices. Asymmetric n-MOSFET＇s have been modeled using a parasitic resistance associated with abnormally structured drain or source and a conventional n-MOSFET model. MEDICI simulation has been done for accuracy of this modeling. Simulated values of reverse as we11 as forward saturation drain current show good agreement with measured values for asymmetric device.

집적도 향상을 위해 사용되는 비대칭 n-MOSFET를 0.35 ㎛ CMOS공정으로 제조하여 그 전기적 특성을 조사고 전기적 모델을 제시하였다. 비대칭형 n-MOSFET는 대칭형 n-MOSFET에 비해 포화영역의 드레인 전류는 감소하였으며, 선형영역의 저항은 증가하였다. 그리고 비대칭형 n-MOSFET에서 보다 낮은 기판 전류가 측정되었다. 측정결과를 찬조하여 비대칭 n-MOSFET를 회로설계에 용이하게 사용할 수 있도록 기존의 대칭형 소자 모델을 개선한 새로운 모델을 제시하였다. 이 모델링의 정확성을 MEDICI 시뮬레이션을 통해 확인하였고, 대부분의 게이트 폭 범위에서 계산된 비대칭 n-MOSFET의 포화 전류 값은 측정값과 거의 일치하였다.

Keywords

References

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