• Applied Microscopy
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• v.41 no.2
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• pp.89-98
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• 2011

Atom Probe Tomography (APT) can provide 3-dimensional information such as position and chemical composition with atomic resolution. Despite the ability of this technique, APT could not be applied for poor conductive materials such as semiconductor. Recently APT has dramatically developed by applying the laser pulsing and combining with Focused Ion Beam (FIB). The invention and combination of these techniques make possible site-specific sample preparation and permit the investigation of various materials including insulators. In this paper, we introduced the recently achieved state of the art applications of APT focusing on Si based FET devices, LED devices, low dimensional materials.

• Journal of Satellite, Information and Communications
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• v.7 no.2
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• pp.18-24
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• 2012

High current behaviors of the extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOSFET) for electrostatic discharge (ESD) protection of high voltage operating LDI (LCD Driver IC) chip are analyzed. Both the transmission line pulse (TLP) data and the thermal incorporated 2-dimensional simulation analysis demonstrate a characteristic double snapback phenomenon after triggering of biploar junction transistor (BJT) operation. Also, background doping concentration (BDC) is proven to be a critical factor to affect the high current behavior of the EDNMOS devices. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.

• Journal of IKEEE
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• v.25 no.2
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• pp.371-375
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• 2021

In this paper, a SiC-based LIGBT structure that can be used at high voltage and high temperature is presented. In order to improve the low current characteristic, a dual-emitter symmetrical around the gate is inserted. In order to verify the characteristics of the proposed device, simulation and design were conducted using Sentaurus TCAD simulation, and a comparative study was conducted with a general LIGBT. In addition, splitting was performed by designating a variable for the length of the N-drift region in order to verify the electrical characteristics of the minority carriers. As a result of the simulation it was confirmed that the proposed dual-emitter structure flows a higher current at the same voltage than the conventional LIGBT.

• ETRI Journal
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• v.11 no.3
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• pp.11-22
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• 1989

Stress에 잘 견딜 수 있는 metal-oxide-semiconductor field effect transistor(MOSFET)의 매우 얇고(10mm 이하) 고신뢰성을 갖는 게이트 절연막을 개발하기 위해서 급속열처리법을 이용하여 제조한 재산화질화산화막의 특성에 관하여 연구하였다. AES 분석에 의하여 8nm 두께의 초기산화막을 질화시킬 때 산화막의 계면이 우선적으로 질화가 일어났으며, 질화된 막을 재산화시킬 때 표면과 계면의 [N]가 감소하였다. 또한 재산화시킬 경우 두께가 약간 증가함을 보였으며, 질화가 강하게 될수록 두께 증가는 크지 않았다. 전기적 특성으로써 I-V 특성과 고주파(1MHz) C-V 특성, 정전류 stress 후의 고주파 C-V 특성 변화 들을 조사한 결과 $950^{\circ}C$ 60초 동안 질화시킨 재산화질화산화막($ONO_L막$) 은 정전류 stress에 대하여 flat band 전압 변화에 계면 상태 밀도(interface state density)변화가 적고, 절연파괴전압(breakdown voltage)특성 등이 우수하게 나타났다.

• The Magazine of the IEIE
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• v.37 no.8
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• pp.31-40
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• 2010

1947년 트랜지스터의 발명을 시작으로 사이리스터, MOSFET 및 IGBT 등의 전력반도체 소자가 개발되면서 산업, 가전 및 통신 등의 다양한 분야에서 실리콘 기반의 전력반도체 소자가 활용되고 있다. 개발 당시에는 10A/수백V 정도의 전류통전능력 및 전압저지능력을 가지고 있었지만, 현재에는 8000A/12kV급의 대용량 소자까지 생산되고 있다. 이러한 전력반도제 소자는 다양한 응용분야에 서 높은 전압 저지능력, 큰 전류 통전 능력 및 빠른 스위칭 특성을 요구하고 있다. 특히 최근의 전력변환장치들은 고온동작특성 및 고효율화에 대한 요구가 더욱 강조되고 있다. 일반적인 실리콘 전력반도체소자는 물질적인 특성한계로 고온에 서의 동작 시 소자 특성이 떨어지는 특징을 보이고 있어 고온 환경에 적합한 전력반도체 소자의 필요성이 증가되어 실리콘에 비해 밴드�b이 넓은 SiC 및 GaN 등의 wide bandgap 반도체 물질의 연구가 활발히 진행되고 있다. 특히 SiC는 단결정 성장을 통한 웨이퍼화가 용이하고 소자 제작공정이 기존 실리콘공정과 유사하여 많은 연구가 진행되었으며 일부 소자에서 상용화가 진행되었다. 본고에서는 현재 활발히 진행되고 있는 탄화규소 전력반도체소자의 기술동향에 대해 소개하고자 한다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.209-212
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• 2001

DRAM과 Logic을 하나의 칩 위에 제조하기 위한 EDL (Embedded DRAM and Logic) 기술에 코발트 실리사이드가 접촉저항을 낮추기 위해 사용된다. 본 연구에서는 코발트 실리사이드 제조에 사용되는 보호막이 CMOS 소자의 전기적 특성에 미치는 영향을 조사하였다. EDL 제조공정이 완전히 진행된 소자에 적용된 실리사이드가 누설전류에 미치는 영향을 비교하였다. 또한 실리사이드 보호막이 전기적 신호의 delay에 미치는 영향을 평가하기 위해, 99개의 CMOS 인버터가 직렬연결되어 있는 평가패턴을 사용하였다. 이상의 결과로 TiN 보호막이 pMOSFET의 전류전달 능력과 그 결과로 생기는 속도지연 측면에서 Ti 보호막보다 우수함을 알 수 있었다.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.88-92
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• 1990

An accurate analytical threshold model is presented for fully depleted SOI which has a Metal-Insulator-Semiconductor-Insulator-Metal structure. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Therefore the model is self-consistent with the measurement scheme. Numerical simulations show good agreement with the model with less than 3% error.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.99-102
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• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.120-126
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• 2006

A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the driver board can be reduced.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.