• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.192-193
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• 2013

본 논문에서는 WBG(Wide Band Gap)특성을 갖는 GaN FET의 과도특성을 분석한다. 먼저, GaN(Gallium Nitride) FET의 공개된 정보를 바탕으로 스위칭 과도 특성과 관련된 파라미터들을 정량적으로 추출하고, GaN FET의 동특성을 반영하는 시뮬레이션 모델을 구성한다. 이 모델을 통하여 Si MOSFET과 비교하여 GaN FET의 성능을 예측한다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.100-109
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• 1995

A new Hydrodynamic model for the high energy tail electrons(Tail Electron Hydrodynamic Model : TEHD) is developed using the moment method. The Monte Carlo method is applied to a $n^{+}-n^{-}-n^{+}$ device to calibrate the TEHD equations. the discretization method and numerical procedures are explained. New models for the impact ionization and injection into the gate oxide using the tail electron density are proposed. The simulated results of the impact ionization rate for a $n^{+}-n^{-}-n^{+}$ device and MOSFET devices, and the gate injection experiment are shown to give good agreement with the Monte Carlo simulation and the measurements.

• Proceedings of the KIPE Conference
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• 2019.11a
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• pp.120-121
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• 2019

본 논문은 GaN 트랜지스터를 적용한 토템폴 PFC(Power Factor Correction)의 디지털 구현을 위한 방법을 제시한다. 특히, GaN 트랜지스터의 낮은 역회복 특성으로 토템폴 PFC의 연속 연속 모드 동작을 가능하게 한다. 토템폴 PFC는 고속 스위칭을 하는 레그를 GaN 트랜지스터를 사용하고, 라인 주파수로 스위칭 하는 레그는 일반적인 MOSFET을 사용하게 된다. 구조적으로 토템폴 PFC는 제로 크로싱에서 전류 스파이크 문제가 발생한다. GaN 트랜지스터는 전류 스파이크에 취약하기 때문에 최소화되어야 한다. 따라서, 본 논문은 디지털 구현에 있어 제로 크로싱에서 소프트 스타트 구현을 통해 이 문제를 최소화 하고, 모의실험을 통해 디지털 구현의 타당성을 입증하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.3
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• pp.332-336
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• 2024

High-energy bandgap material silicon carbide (SiC) is gaining attention as a next-generation power semiconductor material, and in particular, SiC-based MOSFETs are developed as representative power semiconductors to increase the breakdown voltage (BV) of conventional planar structures. However, as the size of SJ (Super Junction) MOSFET devices decreases and the depth of pillars increases, it becomes challenging to uniformly form the doping concentration of pillars. Therefore, a structure with different doping concentrations segmented within the pillar is being researched. Using Silvaco TCAD simulation, a SJ VVD (vertical variation doping profile) MOSFET with three different doping concentrations in the pillar was studied. Simulations were conducted for the width of the pillar and the doping concentration of N-epi, revealing that as the width of the pillar increases, the depletion region widens, leading to an increase in on-specific resistance (R_on,sp) and breakdown voltage (BV). Additionally, as the doping concentration of N-epi increases, the number of carriers increases, and the depletion region narrows, resulting in a decrease in R_on,sp and BV. The optimized SJ VVD MOSFET exhibits a very high figure of merit (BFOM) of 13,400 KW/cm², indicating excellent performance characteristics and suggesting its potential as a next-generation highperformance power device suitable for practical applications.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1489-1498
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• 2015

Gallium nitride (GaN)-based power switching devices, such as high-electron-mobility transistors (HEMT), provide significant performance improvements in terms of faster switching speed, zero reverse recovery, and lower on-state resistance compared with conventional silicon (Si) metal-oxide-semiconductor field-effect transistors (MOSFET). These benefits of GaN HEMTs further lead to low loss, high switching frequency, and high power density converters. Through simulation and experimentation, this research thoroughly contributes to the understanding of performance characterization including the efficiency, loss distribution, and thermal behavior of a 160-W GaN-based synchronous boost converter under various output voltage, load current, and switching frequency operations, as compared with the state-of-the-art Si technology. Original suggestions on design considerations to optimize the GaN converter performance are also provided.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.185-186
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• 2014

본 논문에서는 Si MOSFET 대비 GaN FET의 특성을 비교 분석하고, GaN FET의 장점을 활용할 수 있는 방안을 모색하였다. 그 결과 GaN FET의 우수한 reverse recovery 특성을 활용할 수 있는 토템폴 구조의 브리지리스 부스트 PFC 컨버터를 선정하였고, 선정한 회로의 동작 및 효율을 5.5kW급 프로토타입을 통하여 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.101-101
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• 2007

We fabricated floating gate non-volatile memory devices with Si nanocrystals embedded in $SiN_x$ layer to achieve higher trap density. The average size of Si nanocrystals embedded in $SiN_x$ layer was ranging from 3 nm to 5 nm. The MOS capacitor and MOSFET devices with Si nanocrystals embedded in $SiN_x$ layer were analyzed the charging effects as a function of Si nanocrystals size.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.279-280
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• 2019

본 논문에서는 3KW급 전력변환장치에 적용 가능한 650V급 GaN FET를 사용하여 Half-bridge 구조의 개발보드를 설계 및 제작하고, Double pulse test 실험을 통해 Turn-on 및 off 시스위칭 특성을 분석하였다. 또한 동기정류식 Buck 컨버터에 GaN FET을 적용하고, 유사한 전압 및 전류 정격의 Si MOSFET 소자와 시스템 효율을 비교하여 GaN FET 전력반도체의 성능을 평가하였다.

• Journal of IKEEE
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• v.20 no.2
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• pp.192-195
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• 2016

In this paper, we present a nanopower CMOS bandgap voltage reference working in sub-threshold region without resisters and bipolar junction transistors (BJT). Complimentary to absolute temperature (CTAT) voltage generator was realized by using two n-MOSFET pair with body bias circuit to make a sufficient amount of CTAT voltage. Proportional to absolute temperature (PTAT) voltage was generated from differential amplifier by using different aspect ratio of input MOSFET pair. The proposed circuits eliminate the use of resisters and BJTs for the operation in a sub-1V low supply voltage and for small die area. The circuits are implemented in 0.18um standard CMOS process. The simulation results show that the proposed sub-BGR generates a reference voltage of 290mV, obtaining temperature coefficient of 92 ppm/$^{\circ}C$ in -20 to $120^{\circ}C$ temperature range. The circuits consume 15.7nW at 0.63V supply.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.226-235
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• 1999

To investigate SPICE noise model and the behavior of its parameters, 1/f noise of NMOS devices fabricated by BiCMOS process is measured and compared to the various noise models and measured results. For the long channel devices, bias dependence of the drain current noise power spectral density $S_{Id}$ of NMOS is similar to the previous results. Equivalent gate noise power spectral density $S_{Vg}$ shows weak dependence on the gate and drain voltages in long channel NMOS as the previous results. However, it is shown that most of published noise models are difficult to apply to short channel devices. Therefore, in this study, with comparison of our experimental results, we have tried to find the model of 1/f noise, appropriate for our NMOS device fabricated by BiCMOS process.