• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.55-65
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• 2000

In this paper, we propose a hardware reduced multiplier for DSP applications. In many DSP applications, all of multiplier products were not used, but only upper bits of product were used. Kidambi proposed truncated unsigned multiplier for this idea. in this paper, we adopt this scheme to Booth multiplier which can be used real DSP systems. Also, zero input guarantees zero output that was not provided in previous paper. In addition, we propose bit extension scheme to reduce truncation error more and more. And, we adopted this multiplier to FIR filters for more efficient design.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.148-153
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• 2011

In this paper, an inverse class E frequency multiplier has been designed to generate 5.8 GHz wireless LAN signal by multiplying 2.9 GHz input. The inverse class E frequency multiplier is operating with low inductance value and low peak drain voltage than the class E frequency multiplier. Measurement shows the output power of 21 dBm, the mutiplier gain of 6 dB, and the PAE(Power Added Efficiency) of 35 % with 15 dBm input power.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.69-79
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• 2012

In this paper, we restrict the case as m odd, n=mk, and propose and explicitly exhibit the architecture of a new parallel multiplier over the field GF($2^m$) with a type k Gaussian period which is a subfield of the field GF($2^n$) implements multiplication using the parallel multiplier over the extension field GF($2^n$). The complexity of the time and area of our multiplier is the same as that of Reyhani-Masoleh and Hasan's multiplier which is the most efficient among the known multipliers in the case of type IV.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.925-927
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• 2005

The study is about a finite field multiplying unit, which performs a calculation t-times as fast as the Mastrovito's multiplier architecture, suggesting and using the 2-times faster multiplier architecture. Former studies on finite field multiplication architecture includes the serial multiplication architecture, the array multiplication architecture, and the hybrid finite field multiplication architecture. Mastrovito's serial multiplication architecture has been regarded as the basic architecture for the finite field multiplication, and in order to exploit parallelism, as much resources were expensed to get as much speed in the finite field array multipliers. The array multiplication architecture has weakness in terms of area/performance ratio. In 1999, Parr has proposed the hybrid multipcliation architecture adopting benefits from both architectures. In the hybrid multiplication architecture, the main hardware frame is based on the Mastrovito's serial multiplication architecture with smaller 2-dimensional array multipliers as processing elements, so that its calculation speed is fairly fast costing intermediate resources. However, as the order of the finite field, complex integers instead of prime integers should be used, which means it cannot be used in the high-security applications. In this paper, we propose a different approach to devise a finite field multiplication architecture using Mastrovito's concepts.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.255-258
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• 2004

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only Partial-sum block in the hardware.

• 사회경제평론
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• v.31 no.2
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• pp.1-38
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• 2018

In this study we attempt to quantify the export multiplier to definitively show how exports have undergirded the Korean economy and doing so we will describe how the export multiplier effect has diminished since the global financial crisis in 2008. We also argue that a trend of disinclination in the marginal propensity to consume, one of the determinants of the multiplier, has played an important role in its contraction. In this new, alien economic environment, the kinds of policies that once buttressed the export-led growth strategy of the halcyon days require immediate revision. More policies should implemented that bolster domestic demand, especially consumption, rather than continuing efforts to facilitate supply side-based growth through export-friendly policies.

• International Journal of Computer Science & Network Security
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• v.22 no.9
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• pp.414-426
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• 2022

Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex - 5 and Xilinx Virtex - 7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2¹⁶³), GF(2²³³) and GF(2²⁸³). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex-5 and by 25.13% and 47.75% for Xilinx Virtex-7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex - 5 and Virtex - 7 over GF(2²³³) and GF(2²⁸³)are also very satisfactory.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.10
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• pp.90-99
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• 2009

In this paper, we proposed the new class-E frequency multiplier design that include the highest efficient characteristics. The proposed frequency multiplier is designed for 5.8[GHz] output using the frequency multiplier about 2.9[GHz] input signal. And studying in this paper is for the design and the implementation of the class E frequency multiplier. For the result, the maximum highest efficient characteristics 32[%] which is with output power 24.5[dBm] and 8.5[dB], is shown with frequency multiplier for the 2.9/5.8[GHz] class E. And we applied the linear method to the implemented class E frequency multiplier. As a result, the output spectrum for the linear is upgrade to 12[dB], 12[dB], 13[dB] of the ACPR characteristics on the +11[MHz], +20[MHz], +30[MHz] offset frequency in the center frequency. The result is satisfied with the 3.83[%] of the lineared EVM for the 64-QAM modulated method with the 54[Mbps] transmission velocity. In this paper, we show that the good compensation result of the linearity and the efficiency through the digital pre-linear method of the distortion with the frequency multiplier. Therefore, we suggested the frequency multiplier method are applying to WLAN, cellular, PCS, WCDMA, and etc.