References
-
B. A. Laws and C. K. Rushforth, 'A Cellular Array Multiplier for
$GF(2^m)$ ,' IEEE Trans. Computers, vol. C-20, pp. 1573-1578, Dec. 1971 https://doi.org/10.1109/T-C.1971.223173 - H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yaeh and I. S. Reed, 'A VLSI Design of a Pipelining Reed-Solomon Decoder,' IEEE Trans. Computers, vol. C-34, pp. 393-403, May 1985 https://doi.org/10.1109/TC.1985.1676579
-
C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura and I. S. Reed, 'VLSI Architecture for Computing Multiplications and Inverses in
$GF(2^m)$ ,' IEEE Trans. Computers, vol. C-34, pp. 709-717, Aug. 1985 https://doi.org/10.1109/TC.1985.1676616 -
P. A. Scott, S. E. Tarvares and L. E. Peppard, 'A Fast Multiplier for
$GF(2^m)$ ,' IEEE J. Select. Areas Communications, vol. SAC-4, no. 1, pp. 707-717, Jan. 1986 - I. S. Hsu, T. K. Truong, L. J. Deutsch and I. S. Reed, 'A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases,' IEEE Trans. Computers, vol. C-37, no. 6, pp. 735-739, Jun. 1988 https://doi.org/10.1109/12.2212
-
C. L. Wang and J. L. Lin, 'Systolic Array Implementation of Multipliers for Finite Fields
$GF(2^m)$ ,' IEEE Trans. Circuits and Systems, vol. 38, no. 7, July 1991 - C. K. Koc and B. Sunar, 'Low Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields,' IEEE Trans. Computers, vol. 47, no. 3, pp. 353-356, Mar. 1998 https://doi.org/10.1109/12.660172
- Kiamal Z. Pelanestzi, 'Multiplexer-Based Array Multipliers,' IEEE Trans. Computers, vol. 48, no.1, pp. 15-23, Jan. 1999 https://doi.org/10.1109/12.743408
- H. Wu and M. A. Hasan, 'Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields,' IEEE Trans. Computers, vol. 47, no. 8, pp. 883-887, Nov. 1998 https://doi.org/10.1109/12.707588
- J. J. Wonziak, 'Systolic Dual Basis Serial Multiplier,' IEE Proceeding Computers and Digital Technology, vol. 145, no. 3, pp.237-241, July 1998 https://doi.org/10.1049/ip-cdt:19981938
-
C. S. Yeh, I. S. Reed and T. K. Truong, 'Systolic Multipliers for Finite Field
$GF(2^m)$ ,' IEEE Trans. Computers, vol. C-33, pp. 357-360, Apr. 1984 https://doi.org/10.1109/TC.1984.1676441 - H. Wu and H. A. Hasan and L. F. Blake, 'New Low-Complexity Bit-Parallel Finite Fields Multipliers Using Weekly Dual Basis,' IEEE Trans. Computers, vol. 47, no. 11, pp. 1223-1234, Nov. 1998 https://doi.org/10.1109/12.736433
-
G. Drolet, 'A New Representation of Finite Fields
$GF(2^m)$ Yielding Small Complexity Arithmetic,' IEEE Trans. Computers, vol. 47, no. 9, pp. 938-946, Sept. 1998 https://doi.org/10.1109/12.713313 - A. Halbutogullari and C. K. Koc, 'Mastrovito Multiplier for General Irreducible Polynomials,' IEEE Trans. Computers, vol. 49, no. 5, pp, 503-518, May 2000 https://doi.org/10.1109/12.859542
- Kiamal Z. Pekrnestzi, 'Multiplexer-Based Array Multiplier,' IEEE Trans. Computer, vol. 48, No.1, pp.15-23, Jan. 1999 https://doi.org/10.1109/12.743408
-
C. Y. Lee, E. H. Lu and J. Y. Lee, 'Bit Parallel Systolic Multipliers for
$GF(2^m)$ Fields Defined by All-One and Equally Spaced Polynomials,' IEEE Trans. Computers, vol. 50, no. 5, pp. 385-392, May 2001 https://doi.org/10.1109/12.926154 -
S. W. Wei, 'A Systolic Power-Sum Circuit for
$GF(2^m)$ ,' IEEE Trans. Computers, vol. 43, no. 2, pp.226-229, Feb. 1994 https://doi.org/10.1109/12.262128 -
E. D. Mastrovito, 'VLSI Design for Multiplication on Finite Field
$GF(2^m)$ ,' Proc. International Conference on Applied Algebraic Algorithms and Error-Correcting Code, AAECC-6, Roma, pp. 297-309, July 1998 - R. Lidl, H. Niederreiter and P. M. Cohn, Finite Fields, Addison-Wesley, Reading, Massachusetts, 1983
- S. B. Wicker and V. K. Bhargava, Error Correcting Coding Theory, McGraw-Hill, New York, 1989
-
A. R. Masoleh and M. A. Hasan, 'A New Construction of Massey-Omura Parallel Multiplier over
$GF(2^m)$ ,' IEEE Trans. ?Computers, vol. 51, no. 5, pp. 511-520, May 2002 https://doi.org/10.1109/TC.2002.1004590 - H. Wu, 'Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis,' IEEE Trans. Computers, vol. 51, no. 7, pp.750-758, July 2002 https://doi.org/10.1109/TC.2002.1017695
-
C. L. Wang and J. H. Guo, 'New Systolic Arrays for C+AB2, Inversion, and Division in
$GF(2^m)$ ,' IEEE Trans. Computers, vol. 49, no. 10, pp. 1120-1125, Oct. 2000 https://doi.org/10.1109/12.888047 -
C. H. Kim, S. Oh and J. Lim, 'A New Hardware Architecture for Operation in
$GF(2^m)$ ,' IEEE Trans. Computers, vol. 51, no. 1, pp. 90-92, Jan. 2002 https://doi.org/10.1109/12.980019 -
H. Fan and Y. Dai, 'Fast Bit-Parallel
$GF(2^m)$ Multiplier for All Trinomials,' IEEE Trans. Computer, vol. 54, no. 4, pp.485-490, Apr., 2005 https://doi.org/10.1109/TC.2005.64 -
A. K. Daneshbeh, and M. A. Hasan, 'A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over
$GF(2^m)$ ,' IEEE Trans. Computer, vol. 54, no. 3, pp.370- 380, Mar. 2005 https://doi.org/10.1109/TC.2005.35 -
C. Lee, J. Horng, I. Jou and E. Lu, 'Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of
$GF(2^m)$ ,' IEEE Trans. Computer, vol. 54, no. 9, pp.1061-1070, Sep. 2005 https://doi.org/10.1109/TC.2005.147