Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of High-Speed Parallel Multiplier over Finite Field $GF(2^m)$

유한체 $GF(2^m)$상의 고속 병렬 승산기의 설계

  • Seong Hyeon-Kyeong (School of Computer, Information and Communication Engineering, Sangji University)
  • 성현경 (상지대학교 컴퓨터정보공학부)
  • Published : 2006.09.01
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Abstract

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

본 논문에서는 $GF(2^m)$상에서 표준기저를 사용한 두 다항식의 승산을 비트-병렬로 실현하는 새로운 형태의 고속 병렬 승산기를 제안하였다. 승산기의 구성에 앞서, 피승수 다항식과 기약다항식의 승산을 병렬로 수행한 후 승수 다항식의 한 계수와 비트-병렬로 승산하여 결과를 생성하는 MOD 연산부를 구성하였다. MOD 연산부의 기본 셀은 2개의 AND 게이트와 2개의 XOR 게이트로 구성되며, 이들로부터 두 다항식의 비트-병렬 승산을 수행하여 승산결과를 얻도록 하였다. 이러한 과정을 확장하여 m에 대한 일반화된 회로의 설계를 보였으며, 간단한 형태의 승산회로 구성의 예를 $GF(2^4)$를 통해 보였다. 또한 제시한 승산기는 PSpice 시뮬레이션을 통하여 동작특성을 보였다. 본 논문에서 제안한 승산기는 기본 셀에 의한 MOD 연산부가 반복적으로 이루어짐으로서 차수 m이 매우 큰 유한체상의 두 다항식의 승산에서 확장이 용이하며, VLSI에 적합하다. 또한 승산기회로의 내부에 메모리 소자를 사용하지 않기 때문에 연산과정 중 소자에 의해 발생하는 지연시간이 적으므로 고속의 연산을 수행할 수 있다.

Keywords

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