• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.116-119
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• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.

• Journal of the Korean Mathematical Society
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• v.59 no.4
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• pp.821-841
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• 2022

In this paper, we introduce and study regular rings relative to the hereditary torsion theory w (a special case of a well-centered torsion theory over a commutative ring), called w-regular rings. We focus mainly on the w-regularity for w-coherent rings and w-Noetherian rings. In particular, it is shown that the w-coherent w-regular domains are exactly the Prüfer v-multiplication domains and that an integral domain is w-Noetherian and w-regular if and only if it is a Krull domain. We also prove the w-analogue of the global version of the Serre-Auslander-Buchsbaum Theorem. Among other things, we show that every w-Noetherian w-regular ring is the direct sum of a finite number of Krull domains. Finally, we obtain that the global weak w-projective dimension of a w-Noetherian ring is 0, 1, or ∞.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.9-17
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• 2013

In this paper, we propose a new multiplication algorithm for two polynomials using primitive polynomial with all 1 of coefficient on finite fields GF($2^m$), and design the multiplier with high-speed parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $m^2$ same basic cells that have a 2-input XOR gate and a 2-input AND gate. Since the basic cell have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $D_A+D_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Korean Journal of Microbiology
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• v.43 no.3
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• pp.159-165
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• 2007

For the development of basic genetic materials for specific and effective therapeutic approach to suppress multiplication of hepatitis C virus (HCV), HCV internal ribosome entry site (IRES)-targeting hammerhead ribozyme which activity is allosterically regulated by HCV regulatory protein, NS5B RNA replicase, was developed. The ribozyme targeted most effectively to +382 nucleotide (nt) site of HCV IRES RNA. The allosteric ribozyme was designed to be composed of sequence of RNA aptamer to HCV NS5B, communication module sequence which can transfer structural transition for inducing ribozyme activity upon binding NS5B to the aptamer, and sequence of ribozyme targeting +382 nt of HCV IRES. Noticeably, we employed in vitro selection technology to identify the most appropriate communication module sequence which can induce ribozyme activity depending on the US5B protein. We demonstrated that the ribozyme was nonfunctional either in the absence of any proteins or in the presence of control bovine serum albumin. In sharp contrast, the allosteric ribozyme can induce activity of cleavage reaction with HCV IRES RNA in the presence of the HCV NS5B protein. This allosteric ribozyme can be used as lead compound for specific and effective anti-HCV agent, tool for highthroughput screening to isolate lead chemicals for HCV therapeutics, and ligand for biosensor system for HCV diagnosis.

• Korean Journal of Microbiology
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• v.47 no.3
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• pp.188-193
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• 2011

As a specific and effective therapeutic genetic material against hepatitis C virus (HCV) multiplication, HCV internal ribosome entry site (IRES)-targeting hammerhead ribozyme which activity is allosterically regulated by HCV regulatory protein, NS5B RNA replicase, was constructed. The allosteric ribozyme was composed of sequence of RNA aptamer to HCV NS5B, communication module sequence which can transfer structural transition for inducing ribozyme activity upon binding NS5B to the aptamer, and sequence of ribozyme targeting +382 nucleotide of HCV IRES. With real-time PCR analysis, the ribozyme was found to efficiently inhibit HCV replicon replication in cells. Of note, the allosteric ribozyme was shown to inhibit HCV replicon replication more efficiently than either HCV genome-targeting ribozyme or NS5B aptamer only. This allosteric ribozyme can be used as a lead genetic agent for the specific and effective suppression of HCV replication.

• Kyungpook Mathematical Journal
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• v.51 no.1
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• pp.93-108
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• 2011

A ring R is called left weakly np- injective if for each non-nilpotent element a of R, there exists a positive integer n such that any left R- homomorphism from $Ra^n$ to R is right multiplication by an element of R. In this paper various properties of these rings are first developed, many extending known results such as every left or right module over a left weakly np- injective ring is divisible; R is left seft-injective if and only if R is left weakly np-injective and $_RR$ is weakly injective; R is strongly regular if and only if R is abelian left pp and left weakly np- injective. We next introduce the concepts of left weakly pp rings and left weakly C2 rings. In terms of these rings, we give some characterizations of (von Neumann) regular rings such as R is regular if and only if R is n- regular, left weakly pp and left weakly C2. Finally, the relations among left C2 rings, left weakly C2 rings and left GC2 rings are given.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.194-200
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• 2006

A 26.4 GHz phase locked oscillator(PLO) for communication satellite transponder is developed. The PLO consists of fundamental frequency generation module(FFGM) and frequency multiplication part(FMP). The signal of 26.4 GHz is generated through frequency tripling process of 8.8 GHz fundamental frequency. Phase locking technique using sampling phase detector(SPD) is adopted to design the FFGM. The MMIC tripler and amplifier are also designed for the reduction of the size and mass of FMP. The phase noise characteristics are exhibited as -96 dBc/Hz at 10 tHz offset frequency and -105 dBc/Hz at 100 kHz offset frequency, respectively, with the output power over 11 dBm. All performance parameters are complied with the design requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6A
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• pp.555-561
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• 2002

In this paper, a new designed circuit of highly parallel multiplier using standard basis over $GF(2^m)$ is presented. Prior to construct the multiplier circuit, we provide the Vector Code Generate Module(VCGM) that generate each vector codes for multiplication. Using these VCGMs, we can get all vector codes necessary for operation and modular sum up each independent corresponding basis, respectively. Following the equations in this paper, we can design generalized multiplier to m. For the proposed circuit in this parer, we show the example in $GF(2^4)$ using VCGMs. In this paper, we build a multiplier with VCGMs, AND blocks, and EX-OR blocks. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer then other circuit. We verify the proposed circuit by functional simulation and show its result. Finally, we compare the circuit composition with other works and show its result with a table.