• Title/Summary/Keyword: multiplication module

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ON AGE RINGS AND AM MODULES WITH RELATED CONCEPTS

  • Cho, Yong-Uk
    • East Asian mathematical journal
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    • v.18 no.2
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    • pp.245-259
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    • 2002
  • In this paper, all rings or (left)near-rings R are associative, and for near-ring R, all R-groups are right R action and all modules are right R-modules. First, we begin with the study of rings in which all the additive endomorphisms or only the left multiplication endomorphisms are generated by ring endomorphisms and their properties. This study was motivated by the work on the Sullivan's Problem [14]. Next, for any right R-module M, we will introduce AM modules and investigate their basic properties. Finally, for any nearring R, we will also introduce MR-groups and study some of their properties.

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A low-power VLSI architecture of 4D TCM decoder for ADSL (ADSL용 4D TCM Decoder 저전력 구조 설계 연구)

  • 이금형;김재석
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.871-874
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    • 1999
  • We propose a low complexity M-D(multidimensional) TCM decoder VLSI architecture for ADSL System. We use the shared subset decoder module by modifying the whole decoding procedure. We reduce power consumption by using the MSA (modulo set area) operation, which removes multiplication in 4D metric calculation. Also the proposed TCM decoder reduces chip area. It can be adopted in high-speed xDSL system.

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On Graded Quasi-Prime Submodules

  • AL-ZOUBI, KHALDOUN;ABU-DAWWAS, RASHID
    • Kyungpook Mathematical Journal
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    • v.55 no.2
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    • pp.259-266
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    • 2015
  • Let G be a group with identity e. Let R be a G-graded commutative ring and M a graded R-module. In this paper, we introduce the concept of graded quasi-prime submodules and give some basic results about graded quasi-prime submodules of graded modules. Special attention has been paid, when graded modules are graded multiplication, to find extra properties of these submodules. Furthermore, a topology related to graded quasi-prime submodules is introduced.

Module-theoretic Characterizations of Strongly t-linked Extensions

  • Kim, Hwankoo;Kwon, Tae In
    • Kyungpook Mathematical Journal
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    • v.53 no.1
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    • pp.25-35
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    • 2013
  • In this paper, we introduce and study the concept of "strongly $t$-linked extensions", which is a stronger version of $t$-linked extensions of integral domains. We show that for an extension of Pr$\ddot{u}$fer $v$-multiplication domains, this concept is equivalent to that of "$w$-faithfully flat".

A Study on the Exploratory Learning in Groups Method in Mathematics Education (수학 교과에서의 집단탐구식 수업 방법에 관한 고찰)

  • Hwang, Hye-Jeong
    • Journal of Educational Research in Mathematics
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    • v.12 no.1
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    • pp.1-16
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    • 2002
  • The 7th Curriculum emphasizes that in mathematics classes, mathematical concepts be understood and mathematical problems be solved through student's own exploratory activities including the use of data, manipulatives, andtechnological devices. Following the main idea of the Seventh Mathematics Curriculum, this paper dealt with instructional methods applied suitably and effectively in mathematics classes, and focused on the 'exploratory learning in groups' method in mathematics education. For this purpose, this paper reviewed and summarized theories related to general pedagogy and of mathematics education. Based on the results, it investigated appropriate instructional methods in mathematics education. In particular, this paper focused on studying the exploratory learning method while investigating its properties and understand- ing the relationship between the 'exploratory learning in groups' method and the discussion-centered method. Finally, in order to show the usefulness of the exploratory learning method, this paper developed an example of a teaching module using the exploratory learning method in addition to discussion and lecture-centered methods by the use of manipulatives. The main goal of the module was to make students understand the principle of multiplication of integers.

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A Design of Modular Multiplier Based on Improved Multi-Precision Carry Save Adder (개선된 다정도 CSA에 기반한 모듈라 곱셈기 설계)

  • Kim, Dae-Young;Lee, Jun-Yong
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.4
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    • pp.223-230
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    • 2006
  • The method of implementing a modular multiplier for Montgomery multiplication by using an adder depends on a selected adder. When using a CPA, there is a carry propagation problem. When using a CSA, it needs an additional calculation for a final result. The Multiplier using a Multi-precision CSA can solve both problems simultaneously by combining a CSA and a CPA. This paper presents an improved MP-CSA which reduces hardware resources and operation time by changing a MP-CSA's carry chain structure. Consequently, the proposed multiplier is more suitable for the module of long bit multiplication and exponentiation using a modular multiplier repeatedly.

Design of High-Speed Parallel Multiplier on Finite Fields GF(3m) (유한체 GF(3m)상의 고속 병렬 곱셈기의 설계)

  • Seong, Hyeon-Kyeong
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.2
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    • pp.1-10
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    • 2015
  • In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

A Study on the Implementation of Digital Filters with Reduced Memory Space and Dual Impulse Response Types (기억용량 절약과 순회방식 선택이 가능한 디지털 필터의 구성에 관한 연구)

  • Park, In Jung;Rhee, Tae Won
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.6
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    • pp.950-956
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    • 1986
  • In this paper, a direct addressing mode of a microprocessor is introduced to save memory capacity, and also a dedicated digital filter is constructed to speed up the filter processing and to enable an easy selection of the impulse response types. A theoretical analysis has been conducted on the errors caused by the finite word klength, rounding-off and multiplication procedures. The digital filter designed by the proposed method is made into a module which can function as a 7th-order recursive or a 14-order nonrecursive type with a simples witch operation. The proposed filter is implemented on a printed-circuit board. The frequency characteristics of this filter can be controlled by the multiplication values stored in ROMs. A low-pass, a high-pass and a band-pass filter have been designed and their frequency characteristics are verified by actual measurements. For a order higher filer, two filter modules have been cascaded into an integrated filter of 23rd-order non-recursive low-pass type and a 12th-order recursive multiband type. Their frequency characteirstics have been found to agree with the theory.

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Construction of High-Speed Parallel Multiplier on Finite Fields GF(3m) (유한체 GF(3m)상의 고속 병렬 승산기의 구성)

  • Choi, Yong-Seok;Park, Seung-Yong;Seong, Hyeon-Kyeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.3
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    • pp.510-520
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    • 2011
  • In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and compose the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells that have a mod(3) addition gate and a mod(3) multiplication gate. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

Efficient Semi-systolic Montgomery multiplier over GF(2m)

  • Keewon, Kim
    • Journal of the Korea Society of Computer and Information
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    • v.28 no.2
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    • pp.69-75
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    • 2023
  • Finite field arithmetic operations play an important role in a variety of applications, including modern cryptography and error correction codes. In this paper, we propose an efficient multiplication algorithm over finite fields using the Montgomery multiplication algorithm. Existing multipliers can be implemented using AND and XOR gates, but in order to reduce time and space complexity, we propose an algorithm using NAND and NOR gates. Also, based on the proposed algorithm, an efficient semi-systolic finite field multiplier with low space and low latency is proposed. The proposed multiplier has a lower area-time complexity than the existing multipliers. Compared to existing structures, the proposed multiplier over finite fields reduces space-time complexity by about 71%, 66%, and 33% compared to the multipliers of Chiou et al., Huang et al., and Kim-Jeon. As a result, our multiplier is proper for VLSI and can be successfully implemented as an essential module for various applications.