• Structural Engineering and Mechanics
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• v.41 no.5
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• pp.663-673
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• 2012

A number of mode shape-based structure damage identification methods have been verified by numerical simulations or experiments for on-line structure health monitoring (SHM). However, many of them need a baseline mode shape generated by the healthy structure serving as a reference to identify damages. Otherwise these methods can hardly perform well when multiple cracks conditions occur. So it is important to solve the problems above. By aid of the fractal dimension method (FD), Qiao and Wang proposed a generalized fractal dimension (GFD) to detect the delamination damage. As a modification of GFD, Qiao and Cao proposed the approximate waveform capacity dimension (AWCD) technique to simplify the calculation of fractal and overcome the false peak appearing in the high mode shapes. Based on their valued work, this paper combined and applied the AWCD method and curvature mode shape data to detect multiple damages in beam. In the end, the identification properties of the AWCD for multiple damages have been verified by groups of Monte Carlo simulations and experiments.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09b
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• pp.173-176
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• 2003

본 논문은 기존의 다치오토마타 모델을 적용하여 개성과 감성상태 모델을 제안한다. 기존 다치오토마타 모델을 2개의 오토마타로 분리하여 하나는 감성상태, 다른 하나는 개성을 모델링하는데 이용하였다. 사용자의 내부 감성과 개성은 Valence-Arousal 공간으로 정의된 감성상태를 바탕으로 구성하였고, 2개로 분리된 다치오토마타의 관계를 정의에 따라 구성하여 감성상태와 개성이 동시에 한 개의 오토마타 모델로 모델링 될 수 있는 가능성을 제시하였다.

• Journal of the Korean Institute of Intelligent Systems
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• v.6 no.4
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• pp.3-9
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• 1996

본 논문에서는 Boole 함수를 기호 다치 논리 함수로 확장하여 법-M(Modulus-M)의 수체계를 기본으로 하는 기호 다치 논리 함수에 대한 MacLaurin 전개의 구조적 성질을 분석한다. 그리고 기호 다치 변수의 상태 변화에 따라 이에 사상된 퍼지 규칙을 자동 생성할 수 있는 기법을 제안한다. 또한 이러한 이론과 성질을 기존의 퍼지 추론 기능과 결합하여 동적인 상태 변화에 적응할 수 있는 퍼지 추론 시스템 설계방법을 제안한다.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Journal of information and communication convergence engineering
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• v.18 no.1
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• pp.1-7
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• 2020

This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.41-46
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• 2010

In this paper, the DoA(Direction of Arrival) estimator using unitary MUSIC algorithm is studied. The complex-valued correlation matrix of MUSIC algorithm is transformed to the real-valued one using unitary transform for easy implementation. The eigenvalue and eigenvector are obtained by the combined Jacobi-CORDIC algorithm. CORDIC algorithm can be implemented by only ADD and SHIFT operations and MUSIC spectrum computed by 256 point DFT algorithm. Results of unitary MUSIC algorithm designed by System Generator for FPGA implementation is entirely consistent with Matlab results. Its performance is evaluated through hardware co-simulation and resource estimation.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.2
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• pp.60-69
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• 2010

Lookup-Table (LUT) based fuzzy controller for obstacle avoidance enhances operations faster in multiple obstacles environment. An LUT based fuzzy controller with Positive/Negative (P/N) fuzzy rule base consisting of 18 rules was introduced in our paper$^1$ and this paper shows a 50-rule P/N fuzzy controller for enhancing performance in obstacle avoidance. As a rule, the more rules are necessary, the more buffers are required. This paper suggests LUT sharing method in order to reduce LUT buffer size without significant degradation of performance. The LUT sharing method makes buffer size independent of the whole fuzzy system's complexity. Simulation using MSRDS(MicroSoft Robotics Developer Studio) evaluates the proposed method, and in order to investigate its performance, experiments are carried out to Pioneer P3-DX in the LabVIEW environment. The simulation and experiments show little difference between the fully valued LUT-based method and the LUT sharing method in operation times. On the other hand, LUT sharing method reduced its buffer size by about 95% of full valued LUT-based design.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.189-194
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• 2006

In this paper, design of MUSIC algorithm, which is one of high resolution DOA (direction of arrival) estimation techniques was studied. Generally the complex-valued correlation matrix of MUSIC algorithm is transformed to unitary matrix or matrix expansion for the real hardware implementation. Using the orthogonality between the noise subspace eigenvectors and the steering vectors corresponding to signal component, we estimate DOA with the real-valued computation between steering vectors and noise subspace eigenvectors. The DOA algorithm was designed with VHDL models with considerations of 2 elements and 1 incident wave and its simulation results are derived.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.27-36
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• 1999

This paper proposes algorithms that design the highly parallel multiple-valued logic circuit of DTG(Directed Tree Graph) to be represented by tree structure relationship between input and output of nodes. The conventional Nakajima's algorithms have some problems so that this paper introduce the concept of mathematical analysis based on tree structure to design optimized locally computable circuit. Using the proposed circuit design algorithms in this paper it is possible to design circuit in that DTG have any node number - not to design by Nakajima's algorithms. Also, making a comparison between the circuit design using Nakajim's algorithms and this paper's, we testify that proposed algorithms in this paper optimizes circuit design all case of DTG. Some examples are shown to demonstrate the usefulness of the circuit design algorithm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1216-1224
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• 1988

In this paper, it is presented element generation, addition, multiplication and division algorithm over GF ($2^m$) to calculate multiple-valued logic function. The results of addition and multiplication among these algorithms are applied to the current mode CMOS circuits with ROM structure to design of adder and multiplier on GF ($2^m$). Table-lookup and Euclid's algorithm are required the computation in large quentities when multiple-valued logic functions are developed on GF ($2^m$). On the contrary the presented operation algorithms are prefered to the conventional methods since they are processed without relation to increasing degree m in the general purpose computer. Also, the presened logic circuits are suited for the circuit design of the symmetric multiplevalued truth-tables and they can be implemented addition and multiplication on GF ($2^m$) simultaueously.