• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.22-32
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• 2004

In this paper, we proposed MOVAG(Multi Output Value Array Graphs) based on OVAG by Honghai Jiang to construct multiple valued logic function The MDD(Muliple-valued Decision Diagra) needs many processing time and efforts in circuit design for given multi-variable function by D.M.Miller, and we designed a MOVAG which has reduce the data processing time and low complexity. We propose the construction algorithm and input matrix selection algorithm and we designed the multiple-valued logic circuit using T-gate and verified by simulation results.

• Journal of the Korean Institute of Intelligent Systems
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• v.6 no.4
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• pp.10-16
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• 1996

In this paper, we construct the state table of the automata according to input, state, and change of state and transform that state table into symbolic multi-valued logic formula. Also, we propose an adaptive automata which adapts dynamically change of state aqording to the input string of automata by using the properties of derivative about the symbolic multi-valued logic function. And we analyze the properties of the adaptive automata.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.439-446
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• 1998

This paper presents design of SD adder and PD adder on Multi-Valued Logic. For implementing of Multi-valued logic circuits we use Current-mode CMOS circuits and also use Voltage-mode CMOS circuits partially. The proposed arithmetic circuits was estimated by SPICE simulation. At the SD(Signed-Digit) number presentation applying Multi-Valued logic the carry propagation is always limited to one position to the left this number presentation allows fast parallel operation. The addition method that add M operands using PD( positive digit number) is effective not only for the realization of the high-speed compact arithmetic circuit, but also for the reduction of the interconnection in the VLSI processor. therefor, if we use PD number representation, the high speed processor can be implementation.

• Journal for History of Mathematics
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• v.21 no.1
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• pp.29-44
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• 2008

Fuzzy logic is introduced by Zadeh in 1965. It has been continuously developed by many mathematicians and knowledge engineers all over the world. A lot of papers concerning with the history of mathematics and the mathematical education related with fuzzy logic, but there is no paper concerning with Zadeh. In this article, we investigate his life and papers about fuzzy logic. We also compare two-valued logic, three-valued logic, fuzzy logic, intuisionistic logic and intuitionistic fuzzy sets. Finally we discuss about the expression of intuitionistic fuzzy sets.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.191-200
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• 2002

In this paper, we present the method transforming the interval functions into the truncated difference functions for multi-variable multi-valued functions and implementing the truncated difference functions to the multiple valued logic circuits with uniform patterns using the current mirror circuits and the inhibit circuits by current-mode CMOS. Also, we apply the presented methods to the implementation of circuits for additive truth table of 2-variable 4-valued MOD(4) and multiplicative truth table of 2-variable 4-valued finite fields GF(4). These circuits are simulated under 2${\mu}{\textrm}{m}$ CMOS standard technology, 15$mutextrm{A}$ unit current, and 3.3V power supply voltage using PSpice. The simulation results have shown the satisfying current characteristics. Both implemented circuits using current-mode CMOS have the uniform Patterns and the regularity of interconnection. Also, it is expansible for the variables of multiple valued logic functions and are suitable for VLSI implementation.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.10 no.4
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• pp.287-295
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• 2010

Based on the interval-valued intuitionistic fuzzy hybrid geometric (IIFHG) operator and the interval-valued intuitionistic fuzzy weighted geometric (IIFWG) operator, we investigate the group decision making problems in which all the information provided by the decision-makers is presented as interval-valued in tuitionistic fuzzy decision matrices where each of the elements is characterized by interval-valued intuitionistic fuzzy numbers, and the information about attribute weights is partially known. Anumerical example is used to illustrate the applicability of the proposed approach.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.5 no.2
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• pp.94-98
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• 1987

Multi-Valued(MV) sequential logic circuits are proposed which are free from HAZARD. In this paper, HAZARD is classified Function and Logic HAZARD, and MV switching function in which they are eliminated is described. Also, the basic MV memory elements which can be realized without HAZARD are presented, so that suggest the realizability in the large-scale MV logic system based on these elements.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.3 no.2
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• pp.18-23
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• 1985

This paper develops a new theory of multi-valued switching functions and presents simplification method of the multi-valued combinational circuits for realizing N-valued arithmetic units. Multi-valued adders based on the theory proposed here is presented. Switching funtions to composite 10-valued arithmetic units with BCD input are described which is taken into account of using together with 2-valued logic systems.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.