• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.46-53
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• 2011

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. The CCI is a critical factor which affects occurring data errors in a cell, when surrounding cells are programed. We derived a characteristic equation for CCI considering write procedure of data that is similar with signal equalizing. The model considers the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. We verify the proposed equalizer comparing with the measured data of 1-block MLC NAND flash memory. As the simulation result, the equalizer shows an error correction ratio about 60% under 20nm NAND process.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.424-431
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• 2007

This thesis proposed H-Bridge Multi-Level Inverter for Fluidized Bed Combustion Boiler Secondary Air Fan in 200MW thermal power plant. The adjustable speed drive systems improve the efficiency in lightly load condition and extend the life span of motor by limiting the over current at starting. H-Bridge Multi-level Inverter is composed of the several series low voltage power cell inverters, which have the independent isolated do link, in each phase. KEPRI(Korea Electric Power Research Institute) has successfully completed to develop, install, and commission H-Bridge Multi-level Inverter(6.6kV, 1MVA). This thesis gives a full detail about H-Bridge Multi-level Inverter, proposed boiler DCS(Distributed Control System) logic, and commissioning test result.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.3
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• pp.293-297
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• 2010

Next generation concentrating photovoltaic technologies could have a large-scale impact on world electricity production once they will become economically attractive and grid parity will be reached. Multi-junction solar cells will be characterised by a high value of the cell economical performance index if the cells were able to operate at high concentration level. Concentrating the sunlight by optical devices like lenses or mirrors reduces the area of expensive solar cells or modules, and, moreover, increases their efficiency. Accurate and reliable tracking is an important issue to maintain high the CPV system output power. Further, for high concentration CPV systems, the actual tracker cost is about 20% of the total CPV system cost. In this paper high-concentration is defined as systems using concentration ratios well above 100 times the one sun intensity and trackerlss CPV system studied. Using sphericalness lens and parallel MJ cell connection method were suggested and achieved experiment on a clear day in summer. Development of these high performance multi-junction CPV module promises to accelerate growth in photovoltaic power generation.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.357-359
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• 2018

최근 메모리 반도체 시장은 SD(Secure Digital) 메모리 카드, SSD(Solid State Drive)등의 보급률 증가로 메모리 반도체의 시장이 대규모로 증가하고 있다. 메모리 반도체는 개인용 컴퓨터 뿐만 아니라 스마프폰, 테플릿 PC, 교육용 임베디드 보드 등 다양한 산업에서 이용 되고 있다. 또한 메모리 반도체 생산 업체가 대규모로 메모리 반도체 산업에 투자하면서 메모리 반도체 시장은 대규모로 성장되었다. 플래시 메모리는 크게 NAND-Type과 NOR-Type으로 나뉘며 플로팅 게이트 셀의 전압의 따라 SLC(Single Level Cell)과 MLC(Multi Level Cell) 그리고 TLC(Triple Level Cell)로 구분 된다. SLC 및 MLC NAND-Type 플래시 메모리는 많은 연구가 진행되고 이용되고 있지만, TLC NAND-Tpye 플래시 메모리는 많은 연구가 진행되고 있지 않다. 본 논문에서는 기존에 제안된 SLC 및 MLC NAND-Type 플래시 메모리에서 제안된 큐브 패턴을 TLC NAND-Type 플래시 메모리에서 적용 가능한 큐브 패턴 및 알고리즘을 제안한다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1164-1170
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• 2002

In the ACE2000 MPLS system, MPLS Interface Module(MIM) is composed of an ATM Interface Module and a HFMA performing a packet forwarding. In the MIM, the HFMA RSAR receive cells from the Physical layer and reassemble the cells. And the IP Lookup controller perform a packet forwarding after packet classification. Forwarded packet is segmented into cells in the HFMA TSAR and transfer to the ALMA for the transmission to an ATM cell switch. When the MIM make use of an ATM Interface Module, it directly connect the ALMA with a PHY layer using the UTOPIA Level2 interface. Then, an ALMA performs Master Mode. Also, the HFMA TSAR performs the Master Mode in the MIM. Therefore, the UTOPIA-L2 Controller of the Slave Mode require for interfacing between an ALMA and a HFHA TSAR. In this paper, we implement the architecture and cell control mechanism for the UTOPIA-L2 Controller supporting Multi-ports.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.97-97
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• 2010

We demonstrate the hybrid polymer-quantum dot based multi-functional device (Organic bistable devices, Light-emitting diode, and Photovoltaic cell) with a single active-layer structure consisting of CdSe/ZnS semiconductor quantum-dots (QDs) dispersed in a poly N-vinylcarbazole (PVK) and 1,3,5-tirs- (N-phenylbenzimidazol-2-yl) benzene (TPBi) fabricated on indium-tin-oxide (ITO)/glass substrate by using a simple spin coating technique. The multi-functionality of the device as Organic bistable device (OBD), Light Emitting Diode (LED), and Photovoltaic cell can be successfully achieved by adding an electron transport layer (ETL) TPBi to OBD for attaining the functions of LED and Photovoltaic cell in which the lowest unoccupied molecular orbital (LUMO) level of TPBi is positioned at the energy level between the conduction band of CdSe/ZnS and LiF/Al electrode (band-gap engineering). Through transmission electron microscopy (TEM) study, the active layer of the device has a p-i-n structure of a consolidated core-shell structure in which semiconductor QDs are uniformly and isotropically adsorbed on the surface of a p-type polymer core and the n-type small molecular organic materials surround the semiconductor QDs.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.313-316
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• 2005

본 논문은 대용량 진력변환장치인 멀티-레벨 인버터 시스템에서 출력 전압가변이 손쉬운 HBML(H-Bridge Multi-Level) 인버터의 Master와 Cell 제어기 구성에 관한 것이다. HBML 인버터는 각각의 단위 Cell을 저압에서 사용하는 인버터로 구성하면, 구조적으로 풀-브릿지(Full-Bridge) 인버터를 캐스케이드 방식으로 연결하여 고압출력을 얻을 수 있는 토폴로지이다. 시스템에서 Master와 Cell의 제어 처리를 한곳에 집중하지 않는 분산 제어 방식을 적용하여 통신 Data를 최적화하도록 구성하고, 이를 바탕으로 두 제어기를 고성능 원-칩(One-Chip) DSP로만 설계하였다. 모든 외부 모듈을 내장한 CPU로 제어기가 구성될 경우, 외부 노이즈에 강하며, 추가되는 하드웨어 결선을 최소화할 수 있다. 본 논문에서는 HBML 인버터 출력 생성 시 반드시 요구되는 출력 PWM 동기 및 위상전이(Phase Shift)를 각 제어기 자체에 내장된 모듈만을 이용해서 구현하였다.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.2
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• pp.83-87
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• 2014

This paper introduces a refined opportunistic interference alignment (OIA) technique that uses minimum mean square error (MMSE) detection at the receivers in multiple-input multiple-output multi-cell uplink networks. In the OIA scheme under consideration, each user performs the optimal transmit beamforming and power control to minimize the level of interference generated to the other-cell base stations, as in the conventional energy-efficient OIA. The result showed that owing to the enhanced receiver structure, the OIA scheme shows much higher sum-rates than those of the conventional OIA with zero-forcing detection for all signal-to-noise ratio regions.