• Analytical Science and Technology
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• v.8 no.4
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• pp.539-543
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• 1995

The on-line SPE-HPLC coupling system was developed for the efficient separation and determination of trace pesticides, such as phenoxyacetic acids and esters, and triazines in aqueous solutions. By using the developed SPE-HPLC on-line system, the band broadening usually observed in single precolumn switching mode was greatly reduced, consequently, the quantitative determination of trace pesticides could be achieved, Besides, since most of the analytes preconcentrated by SPE column could be injected directly into HPLC system, the limit of detection can be improved down to ppt level.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.346-347
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• 2020

This paper presents the two combination methods for leakage current reduction in photovoltaic system PCS. The leakage current in the photovoltaic system generated from the parasitic capacitance existing between the photovoltaic system and ground relevance to common mode voltage caused by PWM switching. Firstly, Leakage current reduced by a PWM method using two carriers with 180-degree phase different. Secondly, the leakage current is more reduced by connecting LCL filter to the mid-point of DC link. This combining method is revealed in PSIM simulation with 1 uF parasitic capacitance.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1119-1129
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• 2014

This study proposes a novel five-level three-phase hybrid-clamped converter composed of only six switches and one flying capacitor (FC) per phase. The capacitor-voltage-drift phenomenon of the converter under the classical sinusoidal pulse width modulation (SPWM) strategy is comprehensively analyzed. The average current, which flows into the FC, is a function of power factor and modulation index and does not remain at zero. Thus, a specific modulation strategy based on space vector modulation (SVM) is developed to balance the voltage of DC-link and FCs by injecting a common-mode voltage. This strategy applies the five-segment method to synthesize the voltage vector, such that switching losses are reduced while optional vector sequences are increased. The best vector sequence is then selected on the basis of the minimized cost function to suppress the divergence of the capacitor voltage. This study further proposes a startup method that charges the DC-link and FCs without any additional circuits. Simulation and experimental results verify the validity of the proposed converter, modulation strategy, and precharge method.

• Proceedings of the Korea Water Resources Association Conference
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• 2022.05a
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• pp.85-85
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• 2022

The world's most extensive and active deltas, Louisiana's wetlands, are deteriorating rapidly due to multiple stressors such as the discharge of the Mississippi River, sea-level rise, and coastal retreat, the substantial but spatially and temporally variable impacts. However, the ecological and anthropogenic histories, the mode of environmental changes on a multi-millennial timescale have not been thoroughly documented. This study, a palynology-based multiproxy analysis, investigates hydrological, geological, geochemical, and anthropogenic impacts on southern Louisiana wetlands and a variety of external forcing agents influencing ecological succession. Sediment cores extracted from a small pond on a mangrove-dominate island near Port Fourchon, Louisiana, USA yielded a 4,000-year record. The site has been transformed from freshwater to saline water environments, to a mangrove dominant island over the late Holocene. The multivariate principal component analysis identified the relative strength of external drivers responsible for each ecological shift. The Mississippi River delta cycle (lobe switching) was the dominant driver of ecosystem changes during the late Holocene, while relative sea-level rise, tropical cyclones, climate, and anthropogenic effects have been the main drivers late in the site's history.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.777-788
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• 2014

This paper presents a wide output range, high power efficiency reconfigurable charge pump for driving touch panels with the high resistances. The charge pump is composed of 4-stages and its configuration automatically changes based on the required output voltage level. In order to keep the power efficiency over the wide output voltage range, internal blocks are automatically activated or deactivated by the clock driver in the reconfigurable charge pump minimizing the switching power loss due to the On and Off operations of MOSFET. In addition, the leakage current paths in each mode are blocked to compensate for the variation of power efficiency with respect to the wide output voltage range. This chip is fabricated using $0.18{\mu}m$ BCD process with high power MOSFET options, and the die area is $1870{\mu}m{\times}1430{\mu}m$. The power consumption of the charge pump itself is 79.13 mW when the output power is 415.45 mW at the high voltage mode, while it is 20.097 mW when the output power is 89.903 mW at the low voltage mode. The measured maximum power efficiency is 84.01 %, when the output voltage is from 7.43 V to 12.23 V.

• Journal of IKEEE
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• v.15 no.4
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• pp.330-338
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• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• Journal of IKEEE
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• v.12 no.3
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• pp.176-183
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• 2008

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit as a block. The Saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 95% at 100mA output current. And DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Journal of the Korean Society of Industry Convergence
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• v.20 no.4
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• pp.275-284
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• 2017

As the high-level of the industrial and information age, the electricity become the indispensable element in the daily life including OA, FA, and computer, electric home appliances, and etc. In particular, The continuous use of the high capacity power supply system by applying a Switching Mode Power Supply(SMPS) according to the increase of the secondary side output terminal of the power load of the refrigerator of the home appliance or automation of the plant is pressed. The purpose using the way with this kind of high-capacity altogether is to supply the output voltage and output current regardless of the input voltage or to the external environmental conditions of the secondary-side load fluctuation. In this paper, a combination of a Buck Converter with Boost Converter by making a constant current source to control the inductor current and maintain stable power supply side operating characteristics, when load variations. While maintaining the same characteristics as conventional Buck Converter, and offer a DC-DC Converter system with the new switch pattern having a wide output range capable of operating in Buck-Boost Converter. In addition, after theoretical analysis, we carry out simulations and experiments to verify the validity and performance comparing with a conventional DC-to-DC converter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1397-1408
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• 1998

Service networks for the future communication networks will be combined by the B-ISDN networks. These service networks also will use SS No.7 as the signaling transport network for the control of user requriement service. Therefore, ITU-T recommended B-ISDN signaling layers for SS No.7 as a substitute for N-ISDN MTP signaling layer. In this paper, we propose the implementation structure and describe the characteristics and functions of each signaling layer of SS No.7, which are adapted to ATM switching system, and evaluate a performance. The structure of SSCOP transmission buffer using a linked list and an unit frame length is proposed for SAAL layer and the implementation structure and internal routing method according to the ATM switching system are also proposed for MTP-3b layer. Additionally, we propose the ISUP/B-ISUP level interworking structure using only associated mode, which are presented in the first stage of B-ISDN as the effective internatworking structure of SS No.7 for the circuit related signaling network between the existing N-ISDN networks and B-ISDN networks.