Leakage Current Reduction by a New Combination of PWM Method and Modified connection for 3-level Inverter Photovoltaic PCS

3상 3레벨 태양광 PCS에서 누설전류 저감 기법

  • Seng, Chhaya (Chungnam National University, Department of Electrical Engineering) ;
  • Jo, Jongmin (Chungnam National University, Department of Electrical Engineering) ;
  • Cha, Hanju (Chungnam National University, Department of Electrical Engineering)
  • Published : 2020.08.18

Abstract

This paper presents the two combination methods for leakage current reduction in photovoltaic system PCS. The leakage current in the photovoltaic system generated from the parasitic capacitance existing between the photovoltaic system and ground relevance to common mode voltage caused by PWM switching. Firstly, Leakage current reduced by a PWM method using two carriers with 180-degree phase different. Secondly, the leakage current is more reduced by connecting LCL filter to the mid-point of DC link. This combining method is revealed in PSIM simulation with 1 uF parasitic capacitance.

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