• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.533-538
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• 2001

The barrier height is found to increase from 0.25 to 0.690 eV for Schottky contacts on n-InGaAs using deposition of Ag on a substrate cooled to 77K(LT). Surface analysis leads to an interface model for the LT diode in which there are oxide compounds of In:O and As:O between the metal and semiconductor, leading to behavior as a metal-insulator-semiconductor diode. The metal film deposited t LT has a finer and more uniform structure, as revealed by scanning electron microscopy and in situ metal layer resistance measurement. This increased uniformity is an additional reason for the barrier height improvement. In contrast, the diodes formed at room temperature exhibit poorer performance due to an unpassivated surface and non-uniform metal coverage on a microscopic level.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.83-83
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• 2008

Metal-oxide-silicon-on-insulator (MOSOI) structures were fabricated to study the effect caused by reactive ion etching (RIE) and sacrificial oxidation process on silicon-on-insulator (SOI) layer. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measured C-V curves were compared to the numerical results from 2-dimensional (2-D) simulations. The measurements revealed that the profile of C-V curves significantly changes depending on the SOI surface condition of the MOSOI capacitors. The shift in the measured C-V curves, due to the difference of the fixed oxide charge ($Q_f$), together with the numerical simulation analysis and atomic force microscopy (AFM) analysis, allowed extracting the fixed oxide charges ($Q_f$) in the structures as well as 2-D carrier distribution profiles.

• Journal of the Optical Society of Korea
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• v.17 no.6
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• pp.538-542
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• 2013

We propose a simple model to elucidate the dispersion behavior of spiraling modes on silver nanowire by finding correspondence parameters and building a simple equivalent relationship with the planar insulator-metal-insulator geometry. The characteristics approximated for the proposed structure are compared with the results from an exact solution obtained by solving Maxwell's equation in cylindrical coordinates. The effective refractive index for our proposed equivalent model is in good agreement with that for the exact solution in the 400-2000 nm wavelength range. In particular, when the radius of the silver nanowire is 100 nm, the calculated index shows typical improvements; the average percentage error for the real part of the effective refractive index is reduced to only 5% for the $0^{th}$ order mode (11.9% in previous results) and 1.5% for the $1^{st}$ order mode (24.8% in previous results) in the 400-800 nm wavelength range. This equivalent model approach is expected to provide further insight into understanding the important behavior of nanowire waveguides.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.6
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• pp.346-353
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• 2000

In this paper, we developed 3 dimensional Surface Charge Method which could calculate electric fields inside GIS with a small void in solid insulator or with a metal impurity. We find a metal impurity makes much more non-uniform electric field distribution inside GIS than a small void. We also find electric field is much more increased when a metal impurity is close to solid insulator surface at high voltage conductor.

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.34-40
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• 2021

For developing a switching device of a new concept that cannot be implemented with a semiconductor device, we introduce the Mott insulator-metal transition (IMT) phenomenon occurring out of the semiconductor regime, such as the temperature-driven IMT, the electric-field or voltage-driven IMT, the negative differential resistance (NDR)-IMT switching generated at constant current, and the NDR-based IMT-oscillation. Moreover, the possibilities of new concept IMT switching devices are briefly explained.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1534-1535
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• 2011

Composite hollow insulator consist of an insulating tube bearing the mechanical load protected by an elastomer housing the loads being transmitted to the tube by metal fittings. The core processes are comprised briefly and the electrical and mechanical performance were examined according to the IEC standards. In this study, we have manufactured the composite hollow insulator, and carry out the insulator and busing type test according to the IEC standards. Comprehensive approach followed by the test results would give feasible hollow composite insulator compliable to the IEC standards.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.140-140
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• 2009

The Metal-ferroelectric-semiconductor (MFS) structure has superior advantages such as high density integration and non-destructive read-out operation. However, to obtain the desired electrical characteristics of an MFS structure is difficult because of interfacial reactions between ferroelectric thin film and Si substrate. As an alternative solution, the MFS structure with buffer insulating layer, i.e. metal-ferroelectric-insulator-semiconductor (MFIS), has been proposed to improve the interfacial properties. Insulators investigated as a buffer insulator in a MFIS structure, include $Ta_2O_5$, $HfO_2$, and $ZrO_2$ which are mainly high-k dielectrics. In this study, we prepared the Dy-doped $La_2O_3$ solution buffer layer as an insulator. To form a Dy-doped $La_2O_3$ buffer layer, the solution was spin-coated on p-type Si(100) wafer. The coated Dy-doped $La_2O_3$ films were annealed at various temperatures by rapid thermal annealing (RTA). To evaluate electrical properties, Au electrodes were thermally evaporated onto the surface of the samples. Finally, we observed the surface morphology and crystallization quality of the Dy-doped $La_2O_3$ on Si using atomic force microscopy (AFM) and x-ray diffractometer (XRD), respectively. To evaluate electrical properties, the capacitance-voltage (C-V) and current density-voltage (J-V) characteristics of Au/Dy-doped La2O3/Si structure were measured.

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.64.1-64
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• 2003

A metal-ferroelectric [SrBi$_2$Ta$_2$O$\_$9/ (SBT)-high-k-insulator(PrOx)-semiconductor(Si) structure has been fabricated and evaluated as a key part of metal-ferroelectric-insulator-semiconductor-field-effect-transistor MFIS-FET memory, aiming to improve the memory retention characteristics by increasing the dielectric constant in the insulator layer and suppressing the depolarization field in the SBT layer. A 20-nm PrOx film grown on Si(100) showed both a high of about 12 and a low leakage current density of less than 1${\times}$ 10e-8 A/$\textrm{cm}^2$ at 105 MV/cm. A 400-nm SBT film prepared on PrOx/Si shows a preferentially oriented (105) crystalline structure, grain size of about 130 nm and subface roughness of 3.2 nm. A capacitance-voltage hysteresis is confirmed on the Pt/SBT/PrOx/Si diode with a memory window of 0.3V at a sweep voltage width of 12 V. The memory retention time was about 1 104s, comparable to the conventional Pt/SBT/SiO$\_$x/N$\_$y/(SiO$\_$N/)/Si. The gradual change of the capacitance indicates that some memory degradation mechanism is different from that in the Pt/SBT/SiON/Si structure.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1450-1452
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• 1996

In order to optimize the characteristics of gate insulator for FED(field emission device), we investigated the effect of wet-etching process on the gate insulator for fabrication of FED. We used the general three types of etchants for fabrication of the metal tip FEA(field emitter array), they are MO and oxide etchants to form the gate hole, and Al etchant to remove the release layer. In the result of the breakdown field of the insulator by the measure of the current-voltage characteristics, the breakdown field of insulator for immersing in oxide etchant was rapidly lowering with increasing etching time, but that for immersing in Al etchant was slow lowering. Also, in comparing cleaning with non-cleaning samples, the breakdown field of the cleaning samples was higher than that of non-cleaning samples.

• Journal of the Korean Vacuum Society
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• v.9 no.2
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• pp.162-166
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• 2000

High quality $Si_3N_4$ metal-insulator-metal (MIM) capacitors were realized by plasma enhanced chemical vapor deposition (PECVD). Titanium nitride (TiN) adapted as a diffusion barrier reduced the interfacial reaction between $Si_3N_4$ dielectric layer and aluminum metal electrode showing neither hillock nor observable precipitate along the interface. The capacitance and the current-voltage characteristics of the MIM capacitors showed that the minimum thickness of $Si_3N_4$ layer should be limited to 500 $\AA$ under the present process, below which most of the capacitors were electrically shorted resulting in the devastation of on-wafer yield. According to the transmission electron microscopy (TEM) on the cross-sectional microstructure of the capacitors, the dielectric breakdown was caused by slit-like voids formed at the interface between TiN and $Si_3N_4$ layers when the thickness of $Si_3N_4$ layer was less than 500 $\AA$. Based on the calculation of thermally-induced residual stress, the formation of voids was understood from the mechanistic point of view.