Basic characteristics of metal-ferroelectric-insulator-semiconductor structure using a high-k PrOx insulator layer

  • Noda, Minoru (Department of Physical Science, Graduate School of Engineering Science, Osaka University) ;
  • Kodama, Kazushi (Department of Physical Science, Graduate School of Engineering Science, Osaka University) ;
  • Kitai, Satoshi (Department of Physical Science, Graduate School of Engineering Science, Osaka University) ;
  • Takahashi, Mitsue (Department of Physical Science, Graduate School of Engineering Science, Osaka University) ;
  • Kanashima, Takeshi (Department of Physical Science, Graduate School of Engineering Science, Osaka University) ;
  • Okuyama, Masanori (Department of Physical Science, Graduate School of Engineering Science, Osaka University)
  • Published : 2003.09.01

Abstract

A metal-ferroelectric [SrBi$_2$Ta$_2$O$\_$9/ (SBT)-high-k-insulator(PrOx)-semiconductor(Si) structure has been fabricated and evaluated as a key part of metal-ferroelectric-insulator-semiconductor-field-effect-transistor MFIS-FET memory, aiming to improve the memory retention characteristics by increasing the dielectric constant in the insulator layer and suppressing the depolarization field in the SBT layer. A 20-nm PrOx film grown on Si(100) showed both a high of about 12 and a low leakage current density of less than 1${\times}$ 10e-8 A/$\textrm{cm}^2$ at 105 MV/cm. A 400-nm SBT film prepared on PrOx/Si shows a preferentially oriented (105) crystalline structure, grain size of about 130 nm and subface roughness of 3.2 nm. A capacitance-voltage hysteresis is confirmed on the Pt/SBT/PrOx/Si diode with a memory window of 0.3V at a sweep voltage width of 12 V. The memory retention time was about 1 104s, comparable to the conventional Pt/SBT/SiO$\_$x/N$\_$y/(SiO$\_$N/)/Si. The gradual change of the capacitance indicates that some memory degradation mechanism is different from that in the Pt/SBT/SiON/Si structure.

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