• Journal of the Korean Institute of Intelligent Systems
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• v.6 no.3
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• pp.3-13
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• 1996

In orde to reduce huge memory requirements of multidimensional CMAC problems, building a CMAC system by problem decomposition is investigated. Decomposition is based on resolving a displacement vector in cartesian coordinates into unit vectors that define a few lower-dimensional CMACs in the CMAC system. A CMAC system for an an in verse kinematics problem for a planar manipulator was simulated and the performance of the system was evaluated in terms of training and output quality.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.999-1002
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• 2003

In this study, embodied supervisory system that apply motion detection technique to small web camera and detects watch picture. Motion detection technique that use pixel value of car image that use in existing need memory to store background image. Also, there is sensitive shortcoming at increase of execution time by data process of pixel unit and noise. Suggested technique that compare extracting motion information by block unit to do to have complexion that solve this shortcoming and is strong at noise. Because motion information by block compares block characteristic value of image without need frame memory, store characteristic cost by block of image. Also, can get effect that reduce influence about noise and is less sensitive to flicker etc.. of camera more than motion detection that use pixel value in process that find characteristic value by block unit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.74-79
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• 2004

In this study, embodied supervisory system that apply motion detection technique to small web camera and detects watch picture. Motion detection technique that use pixel value of car image that use in existing need memory to store background image. Also, there is sensitive shortcoming at increase of execution time by data process of pixel unit and noise. Suggested technique that compare extracting motion information by block unit to do to have complexion that solve this shortcoming and is strong at noise. Because motion information by block compares block characteristic value of image without need frame memory, store characteristic cost by block of image. Also, can get effect that reduce influence about noise and is less sensitive to flicker etc.. of camera more than motion detection that use pixel value in process that find characteristic value by block unit.

• Journal of the Korea Society of Computer and Information
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• v.26 no.9
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• pp.1-12
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• 2021

In this paper, we propose a tool called ARCAV (Atomatic Recovery of CUDA Atomicity violation) to automatically repair atomicity violations in GPU (Graphics Processing Unit) program. ARCAV monitors information of every barrier and memory to make actual memory writes occur at the end of the barrier region or to make the program execute barrier region again. Existing methods do not repair atomicity violations but only detect the atomicity violations in GPU programs because GPU programs generally do not support lock and sleep instructions which are necessary for repairing the atomicity violations. Proposed ARCAV is designed for GPU execution model. ARCAV detects and repairs four patterns of atomicity violations which represent real-world cases. Moreover, ARCAV is independent of memory hierarchy and thread configuration. Our experiments show that the performance of ARCAV is stable regardless of the number of threads or blocks. The overhead of ARCAV is evaluated using four real-world kernels, and its slowdown is 2.1x, in average, of native execution time.

• Journal of KIISE
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• v.43 no.9
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• pp.998-1007
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• 2016

In recent years, the cost of automotive ECU (Electronic Control Unit) has accounted for more than 30% of total car production cost. However, the complexity of testing and debugging an automotive ECU is increasing because automobile manufacturers outsource automotive ECU production. Therefore, a large amount of cost and time are spent to localize faults during testing an automotive ECU. In order to solve these problems, we propose a fault localization method in memory for developers who run the integration testing of automotive ECU. In this method, memory is partitioned by utilizing memory map, and fault-suspiciousness for each partition is calculated by utilizing memory update information. Then, the fault-suspicious region for partitions is decided based on calculated fault-suspiciousness. The preliminary result indicated that the proposed method reduced the fault-suspicious region to 15.01(%) of memory size.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.497-508
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• 2008

Mobile Multimedia File System, MNFS, is a file system which extensively exploits NAND FLASH Memory, Since general Flash file systems does not precisely meet the criteria of mobile devices such as MP3 Player, PMP, Digital Camcorder, MNFS is designed to guarantee the optimal performance of FLASH Memory file system. Among many features MNFS provides, there are three distinguishable characteristics. MNFS guarantees, first, constant response time in sequential write requests of the file system, second, fast file system mounting time, and lastly least memory footprint. MNFS implements four schemes to provide such features, Hybrid mapping scheme to map file system metadata and user data, manipulation of user data allocation to fit allocation unit of file data into allocation unit of NAND FLASH Memory, iBAT (in core only Block Allocation Table) to minimize the metadata, and bottom-up representation of directory. Prototype implementation of MNFS was tested and measured its performance on ARM9 processor and 1Gbit NAND FLASH Memory environment. Its performance was compared with YAFFS, NAND FLASH File system, and FAT file system which use FTL. This enables to observe constant request time for sequential write request. It shows 30 times faster mounting time to YAFFS, and reduces 95% of HEAP memory consumption compared to YAFFS.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.775-783
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• 1990

In this paper we implemented the fast thinning unit by modifying the pipeline architecture which was proposed by Stanley R. Sternberg. The unit is useful in preprocessing such as image representation and pattern recognition etc. This unit is composed of interface part, local memory part, address generation part, thinning processing part and control part. In thinning processing part, we shortened the thinning part which performed by means of look up table using window mapping table. Thus we improved the weakness of SAP, in which the number of delay pipeline and window pipeline are equal to image column size. Two independent memorys using tri-state buffer enable the two direction flow of address generated by address generation part. This unit avoids the complexity of architecture and has flexibility of image size by means of simple modification of logic bits.

• Journal of Korea Spatial Information System Society
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• v.10 no.2
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• pp.1-12
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• 2008

Automatic semiconductor manufacture system generating transaction from 50,000 to 500,000 per a second needs storage management system processing very large data at once. A lot of storage management systems are researched for storing very large data. Existing storage management system is typical DBMS on a disk. It is difficult that the DBMS on a disk processes the 500,000 number of insert transaction per a second. So, the DBMS on main memory appeared to use memory. But it is difficultthat very large data stores into the DBMS on a memory because of limited amount of memory. In this paper we propose storage management system using insert transaction of a block unit that can process insert transaction over 50,000 and store data on low storage cost. A transaction of a block unit can decrease cost for a log and index per each tuple as transforming a transaction of a tuple unit to a block unit. Besides, the proposed system come cost to decompress all block of data because the information of each field be loss. To solve the problems, the proposed system generates the index of each compressed block to prevent reducing speed for searching. The proposed system can store very large data generated in semiconductor system and reduce storage cost.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.86-92
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• 2011

In this paper, we propose a novel hardware MPI(Message Passing Interface) unit which supports message passing in multiprocessor system which use distributed memory architecture. MPI Hardware unit processes data synchronization, transmission and completion, and it supports processor non-blocking operation so it reduces overhead according to synchronization. Additionally, MPI hardware unit combines ready entry, request entry, reserve entry which save and manage the synchronized messages and performs the multiple outstanding issue and out of order completion. According to BFM(Bus Functional Model) simulation result, the performance is increased by 25% on many to many communication. After we designed MPI unit using HDL, with synopsys design compiler we synthesized, and for synthesis library we used MagnaChip $0.18{\mu}m$. And then we making prototype chip. The proposed message transmission interface hardware shows high performance for its increase in size. Thus, as we consider low-cost design and scalability, MPI hardware unit is useful in increasing overall performance of embedded MPSoC(Multi-Processor System-on-Chip).

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.121-130
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• 2017

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that does not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read/write operation is a page and the unit of erase operation is a block. Therefore, erase operation is slower than other operations. The AGC, the proposed garbage collection policy focuses on not only garbage collection time reduction for real-time guarantee but also wear-leveling for a flash memory lifetime. In order to achieve above goals, we define three garbage collection operating modes: Fast Mode, Smart Mode, and Wear-leveling Mode. The proposed policy decides the garbage collection mode depending on system CPU usage rate. Fast Mode selects the dirtiest block as victim block to minimize the erase operation time. However, Smart Mode selects the victim block by reflecting the invalid page number and block erase count to minimizing the erase operation time and deviation of block erase count. Wear-leveling Mode operates similar to Smart Mode and it makes groups and relocates the pages which has the similar update time. We implemented the proposed policy and measured the performance compare with the existing policies. Simulation results show that the proposed policy performs better than Cost-benefit policy with the 55% reduction in the operation time. Also, it performs better than Greedy policy with the 87% reduction in the deviation of erase count. Most of all, the proposed policy works adaptively according to the CPU usage rate, and guarantees the real-time performance of the system.