• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.445-446
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• 2012

Recently the interest in wireless power transfer have been studied. ECR (Electromagnetic Coupled Resonance) device, depending on the size of the frequency characteristics of the structure, increasing in volume and larger volume of wireless power transmission device to make use of ECR is a big barrier. So to solve this problem for ECR device miniaturization and high efficiency has been actively studied. In this paper, the size of the device for ECR IM (Impedance Matching) by applying a one-turn coil circuit, remove the device in the form of ECR Network Analyzer measured by removing the one-turn coil has demonstrated the possibility of the device in the form of ECR.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.413-419
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• 1987

In this paper, self-oscillating mixer is designed by small signal S-parameter and series feedback circuit. The input-output matching circuit is accomplished from double stub and additional matching stub. The self-oscillating mixer is oscillating itself and amplifies without any external local oscillator and an intermediate frequency amplifier, so it has advantages in its economical and system simplification. The experimental results show the maximum conversion gain 1.5d B and the noise figure 6.5d B at RF center frequency 4GHz and IF 1.1GHz` output oscillating power 4d Bm, efficiency 13.4%, stability -10MHz/V and -0.5MHz/\ulcornerC at oscillating frequency 5.1GHz.The rejection band loss characteristics in band pass filter and low pass filter are -40d B and -30d B, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.216-224
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• 2009

The endless scaling down of the semiconductor process made the impact of the power network noise on the performance of the state-of-the-art chip a serious design problem. This paper compares the performances of two popular circuit reduction approaches used to improve the efficiency of power network noise analysis: moment matching-based model order reduction (MOR) and node elimination-based MOR. As the benchmarks, we chose PRIMA and R2Power as the matching-based MOR and the node elimination-based MOR. Experimental results indicate that the accuracy, efficiency, and memory requirement of both methods very strongly depend on the structure of the given circuit, i.e., numbers of the nodes and sources, and the number of moments to preserve for PRIMA. PRIMA has higher accuracy in general, while the error of R2Power is also in the acceptable range. On the other hand, PRIMA has the higher efficiency than R2Power, only when the numbers of nodes and sources are small enough. Otherwise, R2Power clearly outperforms PRIMA in efficiency. In the memory requirement, the memory size of PRIMA increases very quickly as the numbers of nodes, sources, and preserved moments increase.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1125-1128
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• 2003

This paper presents the design method of a Colpitts type oscillator with coplanar waveguide(CPW) structures in the range of Ka-band frequency for transmitter and receiver modules. Series short stubs of CPW patterns provide inductances and capacitances in the range of Ka-band which can be expressed as a CLC-$\pi$ equivalent circuit. The experimentation has employed ro4003 substrates as a CPW substrate which has a dielectric constant of 3.38 and a signal and ground space of 100um. A method of momentum simulation for the CPW patterns has performed with an ADS software tool of Hewlett-Packard Corp. Inductance and capacitance circuits of a Colpitts oscillator was interconnected to a MESFET with CPW bend structures of including the input and output impedance matching circuits of the active transistor. Circuit parameters for impedance matching were determined through the network conversion to the equivalent length of CPW transmission lines by using T-network 1 $\pi$-network conversion circuit. A Colpitts oscillator was fabricated on the substrate of a area of 8.5mm x 17.4mm with a MESFET of Fujitsu FMM5704X and CPW series short stubs. The design suggested the possibility of realizing oscillators on a planar surface for the wireless system of tansmitter and receiver modules in the frequency range of 30GHz

• Journal of IKEEE
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• v.22 no.3
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• pp.874-877
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• 2018

Many SMDs (surface mount device) are mounted and mutually connected on a PCB (printed circuit board). System performance degrades when their transmission characteristics are bad. Pads connecting a PCB and SMDs affects PCB transmission characteristics significantly, so pad should be properly aligned to optimize impedance matching. In this paper, effects on PCB transmission characteristics are simulated by pad alignment. When frequency is relatively low, pad alignment seldom affect PCB transmission characteristics, but it affects more and more when frequency or pad size becomes larger. Therefore, pad alignment should be carefully chosen based on target frequency and pad size. Especially, the proposed edge-aligned pad is generally more advantageous over the conventional centered-aligned pad in 12~16 GHz Ku-band frequency.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1959-1960
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.6
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• pp.593-596
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• 2015

In this paper, we design a high efficiency class E power amplifier operating at low drain bias voltage for wireless power transfers. A 13.56 MHz power amplifier is designed at drain bias voltage of 12.5 V using Si MOSFET with the breakdown voltage of 40 V. High quality-factor solenoidal inductor is designed and fabricated for use in output matching circuit to improve output power and efficiency. Input matching circuit simply consists of resistor and inductor to reduce the circuit area and improve the stability. The fabricated power amplifier shows the measured output power of 38.6 dBm with the gain of 16.6 dB and power added efficiency of 89.3 % at 13.56 MHz.

• Journal of electromagnetic engineering and science
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• v.17 no.2
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• pp.108-110
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• 2017

The global positioning system (GPS) is a useful system in civilian and military applications. However, because of the weak signal, GPS receivers are vulnerable to interference caused by unwanted signals or intentional jammers. To alleviate this issue, a controlled reception pattern antenna (CRPA) array can be employed to adaptively place radiation pattern nulls toward the direction of the signal interference. The performance of the CRPA array improves as the number of antenna elements increases. Therefore, antenna miniaturization is highly desirable for CRPA applications. We designed a compact CRPA array based on seven electrically miniaturized microstrip patch antennas (MPAs) on a 5-inch ground platform. We used a non-Foster matching circuit to match efficiently miniaturized MPAs on an FR-4 substrate. Experimental results show that the non-Foster matching circuit significantly improves such elements of antenna performance as return loss and antenna gain. In addition, we confirmed that the mutual coupling of the proposed CRPA array is less than -45 dB.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1188-1191
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• 2003

In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.

• Journal of the Semiconductor & Display Technology
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• v.5 no.4 s.17
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• pp.17-22
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• 2006

In the manufacturing processes of semiconductor, test process is important for quality of products. In the manufacturing process of dynamic memory, memory test is more important. So, automatic test equipment(ATE) is used necessarily. But, according to increase of speed of dynamic memory operation, the rapid test equipment is needed. Impedance matching between ATE and dynamic memory is expected to be an important problem for making a rapid test equipment over 1Gbps. According to increase of speed, inner impedance of ATE also works on important parameter for test. This paper is about the method that is for impedance matching of inner impedance and coaxial cable occurring in manufacturing of ATE. We proved effects of inner impedance by electric theory and verified the method of impedance matching using computer simulation.