• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.141-148
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• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.979-982
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• 2003

Due to the differential transmission technique and low voltage swing, LVDS has been widely used for high speed transmission with low power consumption. This paper presents the design and implementation of interface circuits for 1.5Gb/s operation in 0.35um CMOS technology. The interface circuit ate fully compatible with the low-voltage differential signaling(LVDS) standard. The LVDS proposed in this paper utilizes a sense amplifiers instead of the conventional differential pre-amplifier, which provides a 1.5Gb/s transmission speed with further reduced driver output voltage. Furthermore, the reduced driver output voltage results in reducing the power consumption.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.17-25
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• 2004

In this paper, we propose a new small swing domino logic for low-power consumption. To reduce the power consumption, both the precharge node and the output node swing the range from 0 to $V_{REF}$- $V_{THN}$, where $V_{REF}$=VDD-n $V_{THN}$ (n=1, 2, and 3). This can be done by adding the inverter structure on domino logic that allows a full swing or a small swing on its input terminal without leakage current. Compared to previous works, the proposed structure can save the power consumption of more than 30% for n=0, 1, 2, and 3 in the equation of $V_{REF}$=VDD-n $V_{THN}$. A multiplier applying the proposed domino logic has been designed and fabricated using a 0.35-${\mu}{\textrm}{m}$ n-well CMOS process under 3.3-V supply voltage. Compared with other previous works, it shows a 30% power reduction and a better feature in power-delay product.lay product.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.216-222
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• 2017

The most prominent challenge for MOSFET scaling is to reduce power consumption; however, the supply voltage ($V_{DD}$) cannot be scaled down because of the carrier injection mechanism. To overcome this limit, a new type of field-effect transistor using positive feedback as a carrier injection mechanism (FBFET) has been proposed. In this study we have investigated the electrical characteristics of a $Si_{1-x}Ge_x$ FBFET with one gate and one-sided $Si_3N_4$ spacer using TCAD simulations. To reduce the drain bias dependency, $Si_{1-x}Ge_x$ was introduced as a low-bandgap material, and the minimum subthreshold swing was obtained as 2.87 mV/dec. This result suggests that a $Si_{1-x}Ge_x$ FBFET is a promising candidate for future low-power devices.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.120-124
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• 1995

TCSC can not only increase power flow but also damp low frequency oscillation by controlling firing angles of thyristors. But, a model considering voltage, current firing angles is not derived. This paper used a small signal model considirng these variables which was derived in paper [1]. TCSC model is combined with swing equation. Being related to rotor angles and firing angles of thyristors, current and synchronizing torque coefficient is reformulated. Because firing angles of thyristors can be controlled only twice within one period, swing equation is transformed to discrete time model. It is shown that low frequency oscillation can be damped by controlling firing angles in one machine infinite bus power system.

• Journal of Biomedical Engineering Research
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• v.22 no.4
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• pp.359-368
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• 2001

A new knee-ankle-foot-orthosis(KAFO) which uses an automatically-controlled electromechanical wrap spring clutch for the knee joint was developed in the present study. It was found that the output voltage from the foot switches of the developed KAFO was proportionally increased with respect to the applied load. The output voltage from the infrared sensor also decreased as the knee flexion angle increased. The knee joint system for the new KAFO weighs only 780g lighter than any other commercially available developed system. In addition, the solenoid reduces the reaction time for the automatic control of the knee joint. The static torque of the clutch was measured for three persons, and it satisfied the normal knee extension moment during the pre-swing. Three-dimensional gait analyses for three different gait patterns (normal gait, locked-knee gait, controlled-knee gait) from five normal subjects were conducted. Controlled-knee gait showed the maximum knee flexion angle of 40.56$\pm9.55^{\circ}$ and the maximum knee flexion moment of 0.20$\pm$0.07Nm/kg at similar periods in the normal gait. Our KAFO system satisfies both stability during stance phase and free knee flexion during the swing phase at the proper period during the gait cycle. Therefore, our KAFO system would be very useful in various low extremity orthotic applications.

• Journal of Sensor Science and Technology
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• v.33 no.1
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• pp.12-17
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• 2024

Floating inverter amplifiers (FIAs) have recently garnered considerable attention owing to their high energy efficiency and inherent resilience to input common-mode voltages and process-voltage-temperature variations. Since the voltage gain of a simple FIA is low, it is typically cascaded or cascoded to achieve a higher voltage gain. However, cascading poses stability concerns in closed-loop applications, while cascoding limits the output swing. This study introduces a gain-enhanced FIA that features cross-coupled body biasing. Through simulations, it is demonstrated that the proposed FIA designed using a 28-nm complementary metal-oxide-semiconductor technology with a 1-V power supply can achieve a high voltage gain (> 90 dB) suitable for dynamic open-loop applications. The proposed FIA can also be used as a closed-loop amplifier by adjusting the amount of positive feedback due to the cross-coupled body biasing. The capability of achieving a high gain with minimum-length devices makes the proposed FIA a promising candidate for low-power, high-speed sensor interface systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.1-8
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• 2012

This paper presents a fully-integrated buck converter equipped with packaging inductors. These inductors include parasitic inductances of the bonding wires and lead frames in the package. They have significantly better Q factors than the best on-chip inductors implemented on silicon. This paper also proposes a low-swing gate driver for efficient regulation of high-frequency switching converters. The low-swing driver uses the voltage drop of a diode-connect transistor. The proposed converter is designed and fabricated using a $0.13-{\mu}m$ CMOS process. The fully-integrated buck converter achieves 68.7% and 86.6% efficiency for 3.3 V/2.0 V and 2.8 V/2.3 V conversions, respectively.