• Journal of Korea Society of Digital Industry and Information Management
• /
• v.4 no.1
• /
• pp.9-16
• /
• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• Proceedings of the IEEK Conference
• /
• 2004.06a
• /
• pp.31-34
• /
• 2004

In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power partial correlation Digital Matched Filter for the IMT-2000 communication systems. The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. The proposed architecture was verified by using Xilinx FPGA.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.313-321
• /
• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.6
• /
• pp.58-70
• /
• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.8
• /
• pp.42-45
• /
• 2002

A low power SDRAM output buffer with reduced power line noise and feedthrough current is presented. In multi I/O SDRAM output buffer, feedthrough current as well as the corresponding power dissipation are reduced utilizing proposed undershoot protection circuits. Ground bounce is minimized by the pull down driver using intelligent feedback scheme. Ground bounce noise is reduced by 66.3% and instantaneous and average power are reduced by 27.5% and 11.4%, respectively.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1280-1283
• /
• 2002

This paper discusses issues in VLSI design and implementation of high performance datapath circuits. Of particular concern will he various types of multiplier and adder, which are fundamental to DSP operations. Performance comparison will be provided in terms of sampling speed, layout area, and in particular, power consumption, with techniques that may be applied to reduce power dissipation also suggested. As an example, a low power, high performance recursive filter achieved through bit-level pipelining technique is illustrated

• Transactions of Materials Processing
• /
• v.18 no.8
• /
• pp.589-595
• /
• 2009

The hot forming process of an exhaust CAM for vessel engine was designed by finite element(FE) simulation and experimental analysis. An aim of process design was to achieve the near-net shaped CAM forgings by hot forging process. Based on the compression test results of the low alloy steel, power dissipation map was generated using the the dynamic materials model(DMM). From the map, the initial heating temperature was determined as 1200oC. FE analysis was simulated to predict the formation of forging defects and deformed shape with different forging designs. Optimum process design suggested in this work was made by comparing with the CAM for vessel engine manufactured by actual forging process.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.203-203
• /
• 2013

Low pressure plasmas play a key role in many areas including electronic, aerospace, automotive, biomedical, and toxic waste management industries, and the advantages of the plasma are well known the processing procedure is established. However, the insight behavior of the discharges remains a mystery, even though a simple geometry as capacitive discharges. In this work, we measured RF power dissipation in capacitively coupled plasma (CCP) at various experiment conditions with potential probe and RF current probe. Through the results, we will have a clearer view of the inner nature of the CCP.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.399-402
• /
• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.765-768
• /
• 2003

본 논문에서는 Noise Figure, IP3, Gain, power dissipation들을 최대한 고려하여 간단하면서도 훌륭한 성능을 보이는 PCS용 1.9 GHz CDMA Low Noise Amplifier를 설계하였다. 비록 본 논문에서는 특정한 트랜지스터를 이용하여 설계하였지만, 다른 트랜지스터를 사용하여 이러한 방법으로 설계하여도 무관할 것이다.