• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.89-93
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• 2018

Ceramic substrates applied to power modules of electric vehicles are required to have properties of high thermal conductivity, high electrical insulation, low thermal expansion coefficient and resistance to abrupt temperature change due to high power applied by driving power. Aluminum nitride and silicon nitride, which are applied to heat dissipation, are considered as materials meeting their needs. Therefore, in this paper, the properties of aluminum nitride and silicon nitride as radiator plate materials were compared through a commercial analysis program. As a result, when the process of applying heat of the same condition to aluminum nitride was implemented by simulation, the silicon nitride exhibited superior impact resistance and stress resistance due to less stress and warping. In terms of thermal conductivity, aluminum nitride has superior properties as a heat dissipation material, but silicon nitride is more dominant in terms of reliability.

• Proceedings of the KSR Conference
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• 1999.05a
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• pp.328-335
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• 1999

Three phase full bridge rectifier has been used to obtain dc voltage from three phase ac voltage source. The rectifier system has drawbacks that power factor is low and power flow is unidirectional. Therefore, when dc voltage increases due to regeneration of power the dynamic resister for dissipation of regeneration power must be installed. But three phase PWM converter can be controlled to operate with unity power factor and bidirectional power flow. Therefore when the PWM converter is used as do supply system, the dissipating resistor is not necessary. On this thesis, in order to design a controller having good performance, the hee phase PWM converter is completely modeled by using circuit DQ-transformation and thus a general and simple instructive equivalent circuit is obtained; the inductor set becomes a second order gyrator-coupled system and three phase inverter becomes a transformer as well. Under given phase angle(${\alpha}$) and modulation index(MI) of the three phase inverter, the dc and ac characteristics are obtained by analysis of the transformed equivalent circuit The validity of the equivalent circuit is confirmed through PSPICE simulation. And based on the dc and ac characteristics a controller with unity power factor is proposed.

• Nuclear Engineering and Technology
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• v.56 no.6
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• pp.2352-2366
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• 2024

Reinforced concrete (RC) shear walls with precast steel-concrete composite modular (PSCCM) are strongly recommended in the structural design of nuclear power plants due to the need for a large number of process pipeline crossings and industrial construction. However, the effect of the PSCCM on the mechanical behavior of the whole RC shear wall is still unknown and has received little attention. In this study, three 1:3 scaled specimens, one traditional shear wall specimen (TW) and two shear wall specimens with the PSCCM (PW1, PW2), were designed and investigated under cyclic loadings. The failure mode, hysteretic curve, energy dissipation, stiffness and strength degradations were then comparatively investigated to reveal the effect of the PSCCM. Furthermore, numerical models of the RC shear wall with different PSCCM distributions were analyzed. The results show that the shear wall with the PSCCM has comparable mechanical properties with the traditional shear wall, which can be further improved by adding reinforced concrete constraints on both sides of the shear wall. The accumulated energy dissipation of the PW2 is higher than that of the TW and PW1 by 98.7 % and 60.0 %. The failure of the shear wall with the PSCCM is mainly concentrated in the reinforced concrete wall below the PSCCM, while the PSCCM maintains an elastic working state as a whole. Shear walls with the PSCCM arranged in the high stress zone will have a higher load-bearing capacity and lateral stiffness, but will suffer a higher risk of failure. The PSCCM in the low stress zone is always in an elastic working state.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• Journal of Power Electronics
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• v.7 no.4
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• pp.294-300
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• 2007

This paper deals with a design of a bootstrap power supply using snubber energy regeneration, which is used to power a high-side gate driver of a half-bridge circuit. In the proposed circuit, the energy stored in the low-side snubber capacitor is transferred to the high-side bootstrap capacitor without any magnetic components. Thus, the power dissipation in the RCD snubber can be effectively reduced. The operation principle and design method of the proposed circuit are presented. The experimental results are also provided to show the validity of the proposed circuit.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.492-496
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• 2004

When using a conventional power factor correction circuit, a comparatively huge capacitor is used to boost-up output voltage. It has a large amount of harmonic distortion in the input current waveform. To improve the input current waveform of diode rectifiers, we propose a new operating principle for the power factor correction circuit. Due to the fact that the proposed circuit uses smaller ones and a smaller reactor, the output voltage increases and obtains higher input current waveforms. These are suitable for the harmonics guidelines. The proposed circuit is able to obtain higher power factor and efficiency. Also, it has reduced switching loss and held over-shooting by using an inverter of eliminated dead-time HPWM that has non-linear impedance circuits to make up diodes, capacitance and a reactor. We compared the conventional PWM inverter and proposed HPWM inverters and found that a high input power factor of 97[%] and an efficiency of 98[%] were also obtained.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

• Transactions on Electrical and Electronic Materials
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• v.18 no.5
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• pp.257-260
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• 2017

In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1301-1308
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• 2012

In this paper, the low-power clock generator synchronized with the AC power signal using the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the ADCL, the clock signal of logic circuits should be synchronized with the AC power source. The clock signal for an adiabatic charging and discharging with the AC power signal was generated with the designed Schmitt trigger circuit and ADCL frequency divider using the ADCL buffer. From the simulation result, the power consumption of the proposed clock generator was estimated with approximately 1.181uW and 37.42uW at output 3kHz and 10MHz respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.1068-1076
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• 1996

In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analyog current-mode active filters is proposed. Compared to the current-mode integrator which is proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter is designed with the proposed current-mode integrator. The designed circuits are fabricated using the ORBIT's $1.2{\mu}{\textrm{m}}$ deouble-poly double-metal CMOS n-well process. The experimental results show that the filter has -3dB cutoff frequency at 44.5MHz and 3mW power dissipation with single 3.3V power supply and also $0.12mm^{2}$ chip area.