• 제목/요약/키워드: low-k wafer

검색결과 306건 처리시간 0.033초

모션프로파일의 주파수분석을 통한 웨이퍼 이송로봇의 진동성능 향상 (Improvement of Vibration Performance for Wafer Transfer Robot using Frequency Analysis of Motion Profile)

  • 신동원;윤장규
    • 한국정밀공학회지
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    • 제31권8호
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    • pp.697-703
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    • 2014
  • This paper is study of solving vibration problem occurred in moving hand of wafer transfer robot in semiconductor manufacturing line. Long settling time for decreasing vibration makes low production rate, and moreover the excessive vibration of hand sometimes breaks the wafer in a cassette. The ways of reducing the moving speed and changing the type of motion profile did not help for lessening vibration. Therefore, we analyzed the mechanical property of the hand such as natural frequency, and frequency component of the motion profile currently used in the manufacturing line. In several conditions of motion profile, we found the best condition of which the frequency component in near of natural frequency of the hand is minimal and this induced small vibration in moving hand. The results were verified theoretically and experimentally using frequency analysis.

A study on the fabrication of poly crystalline Si wafer by vacuum casting method and the measurement of the efficiency of solar cell

  • Lee, Geun-Hee;Lee, Zin-Hyoung
    • 한국결정성장학회지
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    • 제12권3호
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    • pp.120-125
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    • 2002
  • Si-wafers for solar cells were cast in a size of $50{\times}46{\times}0.5{\textrm}{mm}^3$ by vacuum casting method. The graphite mold coated by BN powder, which was to prevent the reaction of carbon with the molten silicon, was used. Without coating, the wetting and reaction of Si melt to graphite mold was very severe. In the case of BN coating, SiC was formed in the shape of tiny islands at the surface of Si wafer by the reaction between Si-melt and carbon of the graphite mold on the high temperature. The grain size was about 1 mm. The efficiency of Si solar cell was lower than that of Si solar cell fabricated on commercial single and poly crystalline Si wafer. The reason of low efficiency was discussed.

Ni 캡의 전기도금 및 SnBi 솔더 Debonding을 이용한 웨이퍼 레벨 MEMS Capping 공정 (Wafer-Level MEMS Capping Process using Electrodeposition of Ni Cap and Debonding with SnBi Solder Layer)

  • 최정열;이종현;문종태;오태성
    • 마이크로전자및패키징학회지
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    • 제16권4호
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    • pp.23-28
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    • 2009
  • Si 기판의 캐비티 형성이 불필요한 웨이퍼-레벨 MEMS capping 공정을 연구하였다. 4인치 Si 웨이퍼에 Ni 캡을 전기도금으로 형성하고 Ni 캡 rim을 Si 하부기판의 Cu rim에 에폭시 본딩한 후, SnBi debonding 층을 이용하여 상부기판을 Ni 캡 구조물로부터 debonding 하였다. 진공증착법으로 형성한 SnBi debonding 층은 Bi와 Sn 사이의 심한 증기압 차이에 의해 Bi/Sn의 2층 구조로 이루어져 있었다. SnBi 증착 층을 $150^{\circ}C$에서 15초 이상 유지시에는 Sn과 Bi 사이의 상호 확산에 의해 eutectic 상과 Bi-rich $\beta$상으로 이루어진 SnBi 합금이 형성되었다. $150^{\circ}C$에서 유지시 SnBi의 용융에 의해 Si 기판과 Ni 캡 구조물 사이의 debonding이 가능하였다.

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대기압 플라즈마를 이용한 P타입 태양전지 웨이퍼 도핑 연구 (Study of P-type Wafer Doping for Solar Cell Using Atmospheric Pressure Plasma)

  • 윤명수;조태훈;박종인;김상훈;김인태;최은하;조광섭;권기청
    • Current Photovoltaic Research
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    • 제2권3호
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    • pp.120-123
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    • 2014
  • Thermal doping method using furnace is generally used for solar-cell wafer doping. It takes a lot of time and high cost and use toxic gas. Generally selective emitter doping using laser, but laser is very high equipment and induce the wafer's structure damage. In this study, we apply atmospheric pressure plasma for solar-cell wafer doping. We fabricated that the atmospheric pressure plasma jet injected Ar gas is inputted a low frequency (1 kHz ~ 100 kHz). We used shallow doping wafers existing PSG (Phosphorus Silicate Glass) on the shallow doping CZ P-type wafer (120 ohm/square). SIMS (Secondary Ion Mass Spectroscopy) are used for measuring wafer doping depth and concentration of phosphorus. We check that wafer's surface is not changed after plasma doping and atmospheric pressure doping width is broaden by increase of plasma treatment time and current.

폴리머를 이용한 CIS(CMOS Image Sensor) 디바이스용 웨이퍼 레벨 접합의 warpage와 신뢰성 (A Reliability and warpage of wafer level bonding for CIS device using polymer)

  • 박재현;구영모;김은경;김구성
    • 마이크로전자및패키징학회지
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    • 제16권1호
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    • pp.27-31
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    • 2009
  • 본 논문에서는 웨이퍼 레벨 기술을 이용한 CIS용 폴리머 접합 기술을 연구하고 접합 후의 warpage 분석과 개별 패키지의 신뢰성 테스트를 수행하였다. 균일한 접합 높이를 유지하기 위하여 glass 웨이퍼 상에 dam을 형성하고 접합용 폴리머 층을 patterning하여 Si과 glass 웨이퍼의 접합 테스트를 수행하였다. Si 웨이퍼의 접합온도, 접합 압력 그리고 접합 층이 낮을수록 warpage 결과가 감소하였으며 접합시간과 승온 시간이 짧을수록 warpage 결과가 증가하는 것을 확인하였다. 접합 된 웨이퍼를 dicing 하여 각 개별 칩 단위로 TC, HTC, Humidity soak의 신뢰성 테스트를 수행하였으며 warpage 결과가 패키지의 신뢰성 결과에 미치는 영향은 미비한 것으로 확인되었다.

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Correlation Between Energy Gap and Defect Formation of Al Doped Zinc Oxide on Carbon Doped Silicon Oxide

  • Oh, Teresa;Kim, Chy Hyung
    • Transactions on Electrical and Electronic Materials
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    • 제15권4호
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    • pp.207-212
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    • 2014
  • Aluminum-doped zinc oxide (AZO) films were deposited on SiOC/Si wafer by an RF-magnetron sputtering system, by varying the deposition parameters of radio frequency power from 50 to 200 W. To assess the correlation of the optical properties between the substrate and AZO thin film, photoluminescence was measured, and the origin of deep level emission of AZO thin films grown on SiOC/Si wafer was studied. AZO formed on SiOC/Si substrates exhibited ultraviolet emission due to exciton recombination, and the visible emission was associated with intrinsic and extrinsic defects. For the AZO thin film deposited on SiOC at low RF-power, the deep level emission near the UV region is attributed to an increase of the variations of defects related to the AZO and SiOC layers. The applied RF-power influenced an energy gap of localized trap state produced from the defects, and the gap increased at low RF power due to the formation of new defects across the AZO layer caused by lattice mismatch of the AZO and SiOC films. The optical properties of AZO films on amorphous SiOC compared with those of AZO film on Si were considerably improved by reducing the roughness of the surface with low surface ionization energy, and by solving the problem of structural mismatch with the AZO film and Si wafer.

Design and Fabrication of a Low-cost Wafer-level Packaging for RF Devices

  • Lim, Jae-Hwan;Ryu, Jee-Youl;Choi, Hyun-Jin;Choi, Woo-Chang
    • Transactions on Electrical and Electronic Materials
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    • 제15권2호
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    • pp.91-95
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    • 2014
  • This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

정반 그루브의 형상치수가 사파이어 기판의 연마특성에 미치는 영향 (Effects of Groove Shape Dimension on Lapping Characteristics of Sapphire Wafer)

  • 이태경;이상직;정해도;김형재
    • Tribology and Lubricants
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    • 제32권4호
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    • pp.119-124
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    • 2016
  • In the sapphire wafering process, lapping is a crucial operation in order to reduce the damaged layer and achieve the target thickness. Many parameters, such as pressure, velocity, abrasive, slurry and plate, affect lapping characteristics. This paper presents an experimental investigation on the effect of the plate groove on the material removal rate and roughness of the wafer. We select the spiral pattern and rectangular type as the groove shapes. We vary the groove density by controlling the groove shape dimension, i.e., the groove width and pitch. As the groove density increases to 0.4, the material removal rate increases and gradually reaches a saturation point. When the groove density is low, the pressing load is mostly supported by the thick film, and only a small amount acts on the abrasives resulting to a low material removal rate. The roughness decreases on increasing the groove density up to 0.3 because thick film makes partial participations of large abrasives which make deep scratches. From these results, we could conclude that the groove affects the contact condition between the wafer and plate. At the same groove density, the pitch has more influence on reducing the film thickness than the groove width. By decreasing the groove density with a smaller pitch and larger groove width, we could achieve a high material removal rate and low roughness. These results would be helpful in understanding the groove effects and determining the appropriate groove design.

Ag paste와 실리콘 웨이퍼의 반응성에 따른 태양전지의 전기적 성질 (Electrical Properties of Solar Cells With the Reactivity of Ag pastes and Si Wafer)

  • 김동선;황성진;김형순
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.54-54
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    • 2009
  • Ag thick film has been used for electrode materials with the excellent conductivity. Ag electrode is used in screen-printed silicon solar cells as a electrode material. Compared to photolithography and buried-contact technology, screen-printing technology has the merit of fabricating low-priced cells and enormous cells in a few hours. Ag paste consists of Ag powders, vehicles and additives such as frits, metal powders (Pb, Bi, Zn). Frits accelerate the sintering of Ag powders and induce the connection between Ag electrode and Si wafer. Thermophysical properties of frits and reactions among Ag, frits and Si influence on cell performance. In this study, Ag pastes were fabricated with adding different kinds of frits. After Ag pastes were printed on silicon wafer by screen-printing technology, the cells were fired using a belt furnace. The cell parameters were measured by light I-V to determine the short-circuit current, open-circuit voltage, FF and cell efficiency. In order to study the relationship between the reactivity of Ag, frit, Si and the electrical properties of cells, the reaction of frits and Si wafer on was studied with thermal properties of frits. The interface structure between Ag electrode and Si wafer were also measured for understanding the reactivity of Ag, frit and Si wafer. The excessive reactivity of Ag, frit and Si wafer certainly degraded the electrical properties of cells. These preliminary studies suggest that reactions among Ag, frits and Si wafer should optimally be controlled for cell performances.

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Nano/Micro-friction properties or Chemical Vapor Deposited (CVD) Self-assembled monolayers on Si-wafer

  • Yoon Eui-Sung;Singh R.Arvind;Han Hung-Gu;Kong Hosung
    • 한국윤활학회:학술대회논문집
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    • 한국윤활학회 2004년도 학술대회지
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    • pp.90-98
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    • 2004
  • Nano/micro-scale studies on friction properties were conducted on Si (100) and three self-assembled monolayers (SAMs) (PFOTC, DMDM, DPDM) coated on Si-wafer by chemical vapor deposition technique. Experiments were conducted at ambient temperature $(24{\pm}1^{\circ}C)$ and humidity $(45{\pm}5\%)$. Nano-friction was evaluated using Atomic Force Microscopy (AFM) in the range of 0-40nN normal loads. In both Si-wafer and SAMs, friction increased linearly as a function of applied normal load. Results showed that friction was affected by the inherent adhesion in Si-wafer, and in the case of SAMs the physical/chemical structures had a major influence. Coefficient of friction of these test samples was also evaluated at the micro-scale using a micro-tribotester. It was observed that SAMs had superior frictional property due to their low interfacial energies. In order to study of the effect of contact area on friction coefficient at the micro-scale, friction was measured for Si-wafer and DPDM against Soda Lime balls (Duke Scientific Corporation) of different radii 0.25 mm, 0.5 mm and 1 mm at different applied normal loads $(1500,\;3000\;and\;4800{\mu}N)$. Results showed that Si-wafer had higher friction coefficient than DPDM. Furthermore, unlike that in the case of DPDM, friction was severely influenced by wear in the case of Si-wafer. SEM evidences showed that solid-solid adhesion to be the wear mechanism in Si-wafer.

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