• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.1-6
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• 2014

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of low speed, high area overhead or high wire complexity. Therefore, this paper proposes a new high-speed NCL gate cells designed at transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate cells have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 1998.10a
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• pp.497-504
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• 1998

In the nonlinear dynamic structural analysis, the given ground excitation as an input should be well defined. Because of the lack of recorded accelerograms in Korea, it is required to generate an artificial earthquake by a stochastic model of ground excitation with various dynamic properties rather than recorded accelerograms. It is well own that earthquake motions are generally non-stationary with time-varying intensity and frequency content. Many researchers have proposed non-stationary random process models. Yeh and Wen (1990) proposed a non-stationary stochastic process model which can be modeled as components with an intensity function, a frequency modulation function and a power spectral density function to describe such non-stationary characteristics. This model is based on the simulation for the strong-motion earthquakes with magnitude greater than approximately 5.0~6.0, because it will be not only expected to cause structural damage but also involved the characteristics of earthquake motions. Also, the recorded earthquake motion within this range are still very scarce in Korea. Thus, it is necessary to verify the model by the application of it to the mid-magnitude (approximately 4.0~6.0) earthquakes actually recorded in domestic or foreign area. The purpose of the paper is to generate an artificial earthquake using the model of Yeh and Wen in the area with low seismicity.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.1-6
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• 2014

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

• Journal of Radiation Protection and Research
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• v.34 no.2
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• pp.77-81
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• 2009

An Area Radiation Monitoring System (ARMS) ionization chamber, which had an 11.8 L active volume, was fabricated and performance-tested at KAERI. Low leakage currents, linearities at low and high dose rates were achieved from performance tests. The correlation coefficients between the ionization currents and the dose rates are 1 at high dose rate and 0.99 at low dose rate. In this study, an integration-type ARMS ionization chamber was tested over a year for an evaluation of its long-term stability at a radioisotope (RI) repository of the Young-gwang nuclear power plant. The standard deviation of dose rate of 1 day data and over a 100-days mean value were 6.2 $\mu$R/h and 2.9 $\mu$R/h, respectively. The fabricated ARMS ionization chamber showed stable performance from the results of the long-term tests. Design and performance characteristics of the fabricated ionization chamber for the ARMS from performance-tests are also addressed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.617-620
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• 2001

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier that receives two N-bit numbers and produces an N-bit product by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance (truncation error, area) was analyzed. Since the truncated Booth multiplier omits about half the partial product generators and adders, it has an area reduction by about 35%~40%, compared with non-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 30%~40%, compared with conventional methods.

• Journal of Electrochemical Science and Technology
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• v.4 no.1
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• pp.41-45
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• 2013

Platinum is a well known element which shows a significant electrocatalytic activity in many important applications. In glucose sensor, because of the poisoning effect of reaction intermediates and the low surface area, the electrocatalytic activity towards the glucose oxidation is low which cause the low sensitivity. So, we fabricate a nanoporous PtZn alloy electrode by deposition-dissolution method. It provides a high active surface and a large enzyme encapsulating space per unit area when it used for an enzymatic glucose sensor. Glucose oxidase was immobilized on the electrode surface by capping with PEDOT composite and PPDA. The composite and PPDA also can exclude the interference ion such as ascorbic acid and uric acid to improve the selectivity. The surface area was determined by cyclic voltametry method and the surface structure and the element were analyzed by Scanning Electron Microscope (SEM) and Energy Dispersive X-ray spectroscopy (EDX), respectively. The sensitivity is $13.5{\mu}A/mM\;cm^2$. It is a remarkable value with such simply prepared senor has high selectivity.

• Journal of Biosystems Engineering
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• v.20 no.1
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• pp.13-21
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• 1995

This study was conducted to investigate the cutting mechanism of reciprocating knife of combine harvester. The cutting operation of reciprocating knife with the arrangement of the low-cutting and the double-cutting was demonstrated through cutting pattern diagram which was drawn by computer graphics. Various kinds and dimensions of reciprocating knives were analyzed using the developed program. The results are summarized as follows (1) The low-cutting type reciprocating knife was represented similar cutting characteristics to the standard type, but the maximum stalk-deflection was decreased as 1/2 level of the standard type. And the first ledger plate should be designed shorter than the second ledger plate. (2) The bunching area and the maximum stalk-deflection for the double cutting knife almost were not changed since cutting velocity ratio of 0.6, but the secondary cut were occurred at ratio of 0.8 and increased rapidly over these ratio. (3) The double cutting knife was recommended for the high speed combine, because its bunching area and the maximum stalk-deflection were decreased as 1/2 level of the standard type. (4) In order to maintain the proper cutting mechanism characterized by the bunching area, the maximum stalk-deflection and the secondary cutting length etc., the adequate cutting velocity at forward speed of 0.5㎧ to 1.2㎧ was from 0.3㎧ to 0.96㎧ for the double cutting knives.

• Nuclear Engineering and Technology
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• v.53 no.9
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• pp.2888-2898
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• 2021

Vital area identification (VAI) is an essential procedure for the design of physical protection systems (PPSs) for nuclear power plants (NPPs). The purpose of PPS design is to protect vital areas. VAI has been improved continuously to overcome the shortcomings of previous VAI generations. In first-generation VAI, a sabotage fault tree was developed directly without reusing probabilistic safety assessment (PSA) results or information. In second-generation VAI, VAI model was constructed from all PSA event trees and fault trees. While in third-generation VAI, it was developed from the simplified PSA event trees and fault trees. While VAIs have been performed for NPPs in full-power operations, VAI for NPPs in low-power and shutdown (LPSD) operations has not been studied and performed, even though NPPs in LPSD operations are very vulnerable to sabotage due to the very crowded nature of NPP maintenance. This study is the first to research and apply VAI to LPSD operation of NPP. Here, the third-generation VAI method for full-power operation of NPP was adapted to the VAI of LPSD operation. In this study, LPSD VAI for a few plant operational states (POSs) was performed. Furthermore, the operation strategy of vital areas for both full-power and LPSD operations was discussed. The LPSD VAI method discussed in this paper can be easily applied to all POSs. The method and insights in this study can be important for future LPSD VAI that reflects various LPSD operational states. Regulatory bodies and electric utilities can take advantage of this LPSD VAI method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.71-74
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• 2007

Substitution of the stacked antenna for the normally pressed antenna in the mobile phone was tried for the purpose of decreasing its size. However, reduced size resulted in the difficulties obtaining the targeted characteristics with the bandwidth over 70MHz. The cross-section of the vias in the low temperature co-firing ceramics process was studied to find out effects on the bandwidth characteristics. Circular and rectangular cross-section of the via beneath different types of antenna patterns were simulated. Better bandwidth characteristics were acquired for the larger diameter of the circular section and for the rectangular section as the cross-section area increased. From the viewpoint of the shape of the cross-section, rectangular area showed better characteristics than the circular area with the same longest length in the cross-section.