• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.

• 디지털콘텐츠학회 논문지
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• 제15권3호
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• pp.433-438
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• 2014

본 논문은 배터리와 태스크를 고려한 저전력 알고리듬을 제안하였다. 제안한 알고리듬은 배터리의 용량과 사용 목표 시간에 따른 단위 시간의 소모 전력을 설정한다. 주어진 모든 태스크들의 소모 전력을 계산한다. 태스크들 중에서 소모 전력이 가장 큰 태스크의 소모 전력과 소모 전력이 가장 작은 태스크의 소모 전력의 평균을 구한다. 태스크의 소모 전력의 평균을 단위 시간을 고려하여 다시 소모 전력을 계산한다. 태스크의 평균 소모 전력의 크기가 계산된 소모 전력의 평균보다 작거나 같을 경우 태스크의 평균 소모 전력보다 큰 태스크 들을 대상으로 저전력을 수행한다. 또한, 태스크의 평균 소모 전력의 크기가 계산된 소모 전력의 평균보다 클 경우 계산된 소모 전력의 평균보다 큰 태스크 들을 대상으로 저전력을 수행한다. 저전력은 태스크의 프로세서와 디바이스의 소모 전력을 분할하여 소모 전력이 큰 부분에 대해 저전력을 수행한다. 실험은 배터리를 고려한 저전력 알고리듬인 [6]과 비교하였다. 실험결과 [6]보다 소모 전력이 감소되어 알고리듬의 효율성이 입증되었다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2011년도 추계학술발표대회
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• pp.44-47
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• 2011

In this paper, we propose context-aware based on Low Power Sensing Algorithm. The proposed sensing algorithm reduces power consumptions using low-power sensing algorithms and low-power sensing protocols. Experimental results show that the average power consumption of the proposed method is up to half consumption that of the conventional method.

• 디지털산업정보학회논문지
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• 제5권3호
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1157-1160
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• 2003

We proposed a study on optimal clock period selection algorithm for low power RTL design. The proposed algorithm use the way of maintaining the throughput by reducing supply voltage after improve the system performance in order to minimize the power consumption. In this paper, it select the low power to use pipeline in the transformation of architecture. Also, the algorithm is important the clock period selection in order to maximize the resource sharing. however, it execute the optimal clock period selection algorithm.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.59-63
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• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1165-1168
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• 디지털산업정보학회논문지
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• 제9권1호
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• pp.53-58
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• 2013

In this paper, we proposed low power algorithm for battery residual capacity and a task. Algorithm the mobile devices power of the battery residual capacity for the task to perform power consumption to reduce the frequency alters. Task is different in power consumption according to kinds of in time accomplishment device to use. Adjustment of power consumption analyzes kinds of given tasks from having the minimum power consumption task to having the maximum power consumption task. Control frequency so that power consumption waste to be exposed to battery residual capacity can be happened according to the results analyzed. Experiment the frequency by adjusting power consumption a method to reduce using [7] and in the same environment power of the battery residual capacity consider the task to perform frequency were controlled. Efficiency was proved compare with the experiment results [7]. The experiments results show increment in the number of processing by 45.46% comparing with that [7] algorithm.

• Journal of information and communication convergence engineering
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• 제5권2호
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• pp.131-135
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• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.