• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.11
• /
• pp.101-106
• /
• 2014

This paper presents a wide dynamic range radio-frequency (RF) root-mean-square (RMS) power detector using an automatic gain control (AGC) loop. The AGC loop consists of a variable gain amplifier (VGA), RMS conversion block and gain control block. The VGA exploits dB-linear gain characteristic of the cascade VGA. The proposed circuit utilizes full-wave squaring and generates a DC voltage proportional to the RMS of an input RF signal. The proposed RMS power detector operates from 500MHz to 5GHz. The detecting input signal range is from 0 dBm to -70 dBm or more with a conversion gain of -4.53 mV/dBm. The proposed RMS power detector is designed in a 65-nm 1.2-V CMOS process, and dissipates a power of 5 mW. The total active area is $0.0097mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.4A
• /
• pp.440-449
• /
• 2008

In this paper, we propose a 16-QAM carrier recovery loop which is suitable for the implementation of Inmarsat M4 system receiver. Because the frequency offset of ${\pm}924\;Hz$ on signal bandwidth 33.6 kHz is recommended in Inmarsat M4 system specification, carrier recovery loop having stable operation in the channel environment with large relative frequency offset is required. the carrier recovery loop which adopts only PLL can't be stable in relatively large frequency offset environment. Therefore, we propose a carrier recovery loop which has stable operation in large relative frequency offset environment for Inmarsat M4 system. The proposed carrier recovery loop employed differential filter-based noncoherent UW detector which is robust to frequency offset, CP-AFC for initial frequency offset acquisition using UW signal, and 16-QAM DD-PLL for phase tracking using data signal to overcome large relative frequency offset and achieve stable carrier recovery performance. Simulation results show that the proposed carrier recovery loop has stable operation and satisfactory performance in large relative frequency offset environment for Inmarsat M4 system.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.13 no.5
• /
• pp.11-20
• /
• 2014

Due to the importance of vehicle detector which plays an essential role in generating real-life traffic information, maintaining detector data quality is preeminent in advanced traffic management and information systems (ATMIS). To this end, agencies periodically conduct performance tests on detectors. Detector evaluation is generally performed by comparing baseline data with corresponding detector data. Here, two important things need to be addressed; one is errors (or uncertainties) included in baseline data and the other is the confidence interval concept to represent evaluation results of sample data to corresponding ones of population. To resolve these problems, a new detector evaluation scheme is introduced and the scheme is applied to individual level detector evaluations of loop, video image, and radar detectors. The purpose of individual level evaluation is to eliminate the balancing (or cancelling-out) effects of over- and under-counts. As a consequence, the proposed scheme is proven to be effectively applied to real-world detector evaluations.

• Journal of Korean Society of Transportation
• /
• v.22 no.6
• /
• pp.109-120
• /
• 2004

Since the late of 1990, there have been number of studies on the required number of probe vehicles and/or optimal aggregation interval sizes for travel time estimation and forecasting. However, in general one to five minutes are used as aggregation intervals for the travel time estimation intervals for the travel time estimation and/or forecasting of loop detector system without a reasonable validation. The objective of this study is to deveop models for identifying optimal aggregation interval sizes of loop detector data for travel time estimation and prediction. This study developed Cross Valiated Mean Square Error (CVMSE) model for the link and route travel time forecasting, The developed models were applied to the loop detector data of Kyeongbu expressway. It was found that the optimal aggregation sizes for the travel time estimation and forecasting are three to five minutes and ten to twenty minutes, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.1
• /
• pp.22-28
• /
• 2009

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.6 no.2
• /
• pp.34-44
• /
• 2007

Many urban cities deployed ITS technologies to improve the efficiency of traffic operation and management including a real-time franc control system (i.e., COSMOS). The system adopted loop detector system to collect traffic information such as volume, occupancy time, degree of saturation, and queue length. This paper investigated the applicability of detector information within COSMOS to represent the congestion level of the links. Initially, link travel times obtained from the field study were related with each of detector information. Results showed that queue length was highly correlated with link travel time, and direct link travel time estimation using the spot speed data produced high estimation error rates. From this analysis, a procedure was proposed to estimate congestion level of the links using both degree of saturation and queue length information.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.2
• /
• pp.46-52
• /
• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.10
• /
• pp.1163-1171
• /
• 2007

In this paper, the design techniques required to design heterodyned OPLL such as frequency-phase deference detector, loop filter and phase noise of semiconductor laser are presented. Through the experiments with the calculated parameters, we confirmed that the frequency-phase difference detector simply develops an error component that is proportional to the frequency-phase difference between heterodyned optical signals. The achieved frequency-phase locking range of the input laser diode frequency is around ${\pm}150MHz$. This paper describes the details of the designed as well as experimental results.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.19 no.2
• /
• pp.38-50
• /
• 1982

A new type of digital phase-locked loop (DPLL) called the modified digital Costas loop is proposed and analyzed. The main feature of the proposed loop is that the phase error detector of the loop has linear characteristic. This results from the use of the tan-1 (.) function in the loop. Accordingly, the DPLL can be characterized by a modulo-2$\pi$ linear difference equation. This paper is diveide into two parts. In Part I we describe the proposed system, and analyze the performance of the first-and second-order loops in the absence of noise by the Phase Plane technique. The locking ranges for the DPLL's to achieve exact locking independently of initial conditions have been obtained in closed forms. Also, the false lock and oscillation phenomena occurring under some initial conditions have been considered. These results have been verified by computer simulation. In Part ll we analyze the proposed system in the presence of noise. The steady state probability density function, mean and variance of the phase error have been obtained by solving the Chapman-Kolmogorov equation. These results will be presented in Part ll.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.198-201
• /
• 2014

The phase frequency detector (PFD) is one of the most important building blocks of a phase locked Loop (PLL). Due to blind-zone problem, the detection range of the PFD is low. The blind zone of a PFD directly depends upon the reset time of the PFD and the pre-charge time of the internal nodes of the PFD. Taking these two parameters into consideration, a PFD is designed to achieve a small blind zone closer to the limit imposed by process-voltage-temperature variations. In this paper an enhanced architecture is proposed for dynamic logic PFD to minimize the blind-zone problem. The techniques used are inverter sizing, transistor reordering and use of pre-charge transistors. The PFD is implemented in 180 nm technology with supply voltage of 1.8 V.