• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.438-441
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• 2000

In this paper, Turbo rode is describing a performance near the Shannon's channel capacity limit. So, basic theory of turbo code and MAP,Log-MAP decoding algorithm was arranged. The foundation of this using VHDL, Log-MAP turbodecoder was implemented by Altera´s FLEX10K CPLD.

• Journal of Power Electronics
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• v.10 no.3
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• pp.277-284
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• 2010

This paper presents a novel hybrid carrier based space vector modulation for cascaded multilevel inverters. The proposed technique inherits the properties of carrier based space vector modulation and the fundamental frequency modulation strategy. The main characteristic of this modulation are the reduction of power loss, and improved harmonic performance. The carrier based space vector modulation algorithm is implemented with a TMS320F2407 digital signal processor. A Xilinx Complex Programmable Logic Device is used to develop the hybrid PWM control algorithm and it is integrated with a digital signal processor for hybrid carrier based space vector PWM generation. The inverter offers less weighted total harmonic distortion and it operates with equal electrostatic and electromagnetic stress among the power devices. The feasibility of the proposed technique is verified by spectral analysis, simulation, and experimental results.

• Proceedings of the KIEE Conference
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• 1999.07b
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• pp.976-978
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• 1999

Recently PWM invertor is broadly used for control of induction motor. The invertor is able to generate sin wave current from high speed switching power device such as IGBT. However the invertor is disturbed by dead time inevitably needed to prevent a short of the DC link voltage, and the dead time mainly causes distortions of the output current. In this Paper the dead time compensation method which corrects the voltage error from dead time, and Min Max algorithm enlarging the operating voltage of PWM were Proposed. This method can be implemented by software programming without any additional hardware circuit. The proposed algorithms were implemented by DSP(TMS320C31, 40MHz) and FPGA(QL2007, Quick Logic) described in VHDL. and applied to 3 phase induction motor(2.2 KW) to show the superior performance

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.499-500
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• 2008

In this paper, we design and implement the monolithic power factor correction IC for system power modules using a high voltage(50V) CMOS process. The power factor correction IC is designed for power applications, such as refrigerator, air-conditioner, etc. It includes low voltage logic, 5V regulator, analog control circuit, high-voltage high current output drivers, and several protection circuits. And also, the designed IC has standby detection function which detects the output power of the converter stage and generates system down signal when load device is under the standby condition. The simulation and experimental results show that the designed IC acts properly as power factor correction IC with efficient protective functions.

• Journal of Korean Association for Spatial Structures
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• v.13 no.3
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• pp.91-98
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• 2013

A multi-input single-output (MISO) semi-active control systems were studied by many researchers. For more improved vibration control performance, a structure requires more than one control device. In this paper, multi-input multi-output (MIMO) semi-active fuzzy controller has been proposed for vibration control of seismically excited small-scale buildings. The MIMO fuzzy controller was optimized by multi-objective genetic algorithm. For numerical simulation, five-story example building structure is used and two MR dampers are employed. For comparison purpose, a clipped-optimal control strategy based on acceleration feedback is employed for controlling MR dampers to reduce structural responses due to seismic loads. Numerical simulation results show that the MIMO fuzzy control algorithm can provide superior control performance to the clipped-optimal control algorithm.

• Journal of IKEEE
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• v.11 no.4
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• pp.315-321
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• 2007

The fast charging photoflash capacitor charger with wide range current limiter is presented. By using proposed control logic block and wide range current limiter, the photoflash capacitor charger can reduce charging time and control life of battery for user convenience. The proposed photoflash capacitor charger has 3s charging time at 3.3V battery voltage, 1.2A current limit condition. It is well-suited for portable device application like digital camera, digital video camera, and mobile phone with camera.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.309-312
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• 2001

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.925-928
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• 1999

A multi-channel gas leakage monitoring system was designed and fabricated by using CPLD(complex Programmable Logic .Device) for monitoring and controlling the leakage of natural gas from supplying-pipes under the ground. Fabricated SnO$_2$thick film gas sensor elements were attached on safeguard steel plate of natural gas supplying pipes, and the local monitoring system in this study received the signal from the gas sensors. The monitoring system was implemented by using CPLD chip to reduce the development time and implement simple one chip system. The time division multi-channel system received the input signal from individual gas sensor at one of divided times by multiplexor and signal processed sequentially. The system reduced the size of peripheral circuit resulted in implementation of creditable simple system.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2005.03a
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• pp.469-476
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• 2005

To date, many viable smart base isolation systems have been proposed. In this study, a novel friction pendulum system (FPS) and an MR damper are employed as the isolator and supplemental damping device, respectively. A fuzzy logic controller (FLC) is used to modulate the MR damper. A genetic algorithm (GA) is used for optimization of the FLC. The main purpose of employing a GA is to determine appropriate fuzzy control rules as well to adjust parameters of the membership functions. To this end, a GA with a local improvement mechanism is applied. Neuro-fuzzy models are used to represent dynamic behavior of the MR damper and FPS. Effectiveness of the proposed method for optimal design of the FLC is judged based on computed responses to several historical earthquakes. It has been shown that the proposed method can find appropriate fuzzy rules and the GA-optimized FLC outperforms not only a passive control strategy but also a human-designed FLC and a conventional semi-active control algorithm.

• Journal of the Optical Society of Korea
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• v.20 no.4
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• pp.464-469
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• 2016

All-optical non-return-to-zero (NRZ) -to- return-to-zero (RZ) data-format conversion has been successfully demonstrated using a semiconductor optical amplifier in a fiber-loop mirror (so-called SOA-loop mirror) with a continuous-wave (CW) holding beam. The converted RZ signal after pulse compression has been used to create a 40 Gb/s OTDM (Optical Time Division Multiplexing) signal. Here is proposed an NRZ-to-RZ conversion method without any additional optical clocks, unlike conventional methods based on optical AND logic. In addition, it has the merit of operating at various bit-rate speeds without any controlling device. Moreover, it has a simple structure, and it can be used for all-optical bit-rate-flexible clock recovery.