• 한국정밀공학회지
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• 제23권7호
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• pp.138-145
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• 2006

A nanopatterning technique was proposed and demonstrated for low cost and mass productive process using the scanning probe lithography (SPL) and soft lithography. The nanometer scale structure is fabricated by the localized generation of oxide patterning on the H-passivated (100) silicon wafer, and soft lithography was performed to replicate of nanometer scale structures. Both height and width of the silicon oxidation is linear with the applied voltagein SPL, but the growth of width is more sensitive than that of height. The structure below 100 nm was fabricated using HF treatment. To overcome the structure height limitation, aqueous KOH orientation-dependent etching was performed on the H-passivated (100) silicon wafer. Soft lithography is also performed for the master replication process. Elastomeric stamp is fabricated by the replica molding technique with ultrasonic vibration. We showed that the elastomeric stamp with the depth of 60 nm and the width of 428 nm was acquired using the original master by SPL process.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.633-636
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• 2005

Imprint lithography is a promising method for high-resolution and high-throughput lithography using low-cost equipment. As with other nanoimprint methods, ultraviolet-nanoimprint lithography (UV-NIL) resolution appears to be limited only by template resolution, and offers a significant cost of ownership reduction when compared to other next generation lithography (NGL) methods such as EUVL and 157 nm lithography. The purpose of this paper is to suggest optimum values of control parameters of Imprio 100 manufactured by Molecular Imprint, Inc., which is the first commercially available UV-NIL tool, for sound nanoimprint. UV-NIL experiments were performed on Imprio 100 to find dispensing recipe for avoiding air entrapment. Dispensing recipe related to residual layer thickness and uniformity was optimized and 40 nm thick residual layer was achieved.

• 센서학회지
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• 제28권4호
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• pp.251-255
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• 2019

We propose a two-step lithography process to minimize edge-bead issues caused by thick photoresist (PR) coating. In the conventional PR process, the edge bead can be efficiently removed by applying an edge-bead removal (EBR) process while rotating the silicon wafer at a high speed. However, applying conventional EBR to the production of desired PR mold with unique negative patterns cannot be used because a lower rpm of spin coating and a lower temperature in the soft bake process are required. To overcome this problem, a two-step lithography process was developed in this study and applied to the fabrication of a polydimethylsiloxane (PDMS) film having super-hydrophobic characteristics. Following UV exposure with a first photomask, the exposed part of the silicon wafer was selectively removed by applying a PR developer while rotating at a low rpm. Then, unique PR mold structures were prepared by employing an additional under-exposure process with a second mask, and the mold patterns were transferred to the PDMS. Results showed that the fabricated PDMS film based on the two-step lithography process reduced the height difference from 23% to 5%. In addition, the water contact angle was greatly improved by spraying of hydrophobic nanosilica on the dual-scaled PDMS surface.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 추계학술대회 논문집
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• pp.499-500
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• 2007

• 제어로봇시스템학회논문지
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• 제14권4호
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• pp.332-335
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• 2008

PMMA light guiding plate with nano pattern was fabricated by nano imprint lithography method. A silicon mold for electroplating of nickel was fabricated by conventional photolithography process. A nickel stamp for nano imprint lithography was fabricated by electroplating process using silicon mold. The nano imprint lithography was performed on PMMA plate at $140^{\circ}C$ under pressure of 20kN. The nano pattern on PMMA plate was investigated using FE-SEM. It is shown that the patterns were well transferred for several steps and the nano imprint lithography method could be applied for fabricating patterns of light guiding plate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• 한국진공학회지
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• 제5권4호
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• pp.309-314
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• 1996

VLSI 공정에 평탄화를 위하여 사용되는 SOG과 AFM lithography에 resist 재료로서 이용되는 것이 확인되었다. 이에 기초하여, 본 연구는, SOG가 VLSI lithography 공정에 이용되기 위한 coating막 두께의 가변, 현상을 위한 etching time 및 etching selectivity의 가변, 패턴의 크기에 따르는 적정 공급전압을 선택 등으로 공정의 여유도를 크게 개선하였다. 공급전압 60V, FE 전류량 5nA로서 800$\AA$의 fine 패턴을 얻었다. 차세대 DRAM 제작공정 기술을 위한 AFM lithography에 있어서, SOG의 사용은 공정 여유도가 양호함에 의하여 크게 전망되는 기술이 될 것이다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.196-198
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• 2003

Classical lithography in semiconductor employs stepper technologies. Limits of this technology are clearly seen at structures below 100nm. Nano-imprinting lithography is a new method for generating patterns in submicron range at reasonable cost. In order to manufacture nano-imprinting lithography(NIL) equipment, several NIL manufacturers have been developing key technologies for realization of nano-imprinting process, recently. In this paper, we've been describe state-of-the-art and technology trends for nano-imprinting lithography equipments.

• 한국진공학회지
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• 제19권2호
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• pp.96-104
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• 2010

NIL, S-FIL과 같은 각인 기술(Imprinting lithography)를 적용하기 위한 투명하고 단단한 복제 틀(replica hard mold)을 제작하여 고가의 원판(master)와 패턴이 형성되는 기판과의 접촉을 근본적으로 방지해 경제적인 공정이 가능함을 제안한다. 실리콘 웨이퍼(Si wafer)와 같은 원판(master)과 패턴 형성 시 사용되는 기판과 직접적인 접촉을 방지하기 위해 우선 액상 공정을 이용하여 비접착성 표면처리된 고분자 복제(polymer copy)를 매개체(carrier)로 단단한 복제 틀을 제작한다. 이렇게 제작된 단단한 복제 틀(replica hard mold)는 유리와 거의 같은 강도와 투명도를 나타내며, 각인 공정(imprinting process)에서 석영 틀, 실리콘 웨이퍼(quartz mold, Si wafer)과 같이 값비싼 원판(master)의 직접 사용을 대체하여 성공적으로 패턴을 구현할 수 있다.

• 전자공학회논문지A
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• 제33A권7호
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• pp.198-204
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• 1996

Electron beam lithography is one of the importnat technologies which can delineate deep submicron patterns. REcently, electron beam lithography is being applied in delineating the critical layers of semiconductor device fabrication. In this paper, we present a development simulation program for electron beam lithography and study the development profiles of resist when resist is exposed by the electron beam. Experimentally, the development parameter of positive and negative resists are measured and the data is applied to input parameter of the simulation program. Also simulation results are compared of the process results in the view of resist profiles. As a result, for PMMA and SAL 601 resist, the trend of simulation to the values of process parameters agree with real process results very well, so that the process results can be predicted by the simulation.