• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1270-1273
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• 1997

We have investigated the latchup characteristics of BL/BILLI retrograde twin well CMOS that has the high energy ion implanted buried layer to intend for more improvement of latchup compare to conventional retrograde well and BILLI structures. We explored the dependence of various latchup characteristics such as n+ trigger latchup and p+ trigger latchup on the buried layer implant doses. We show various DC latchup characteristics that allow us to evaluate each technology and suggest guidelines for the reduction of latchup susceptibility.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.3079-3084
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• 2014

When an integrated circuit device is burned out under high-intense radiation and device-level simulation that usually requires manufacturer's proprietary information is not available, experimental conformation of a failure mechanism is often the only choice. To distinguish Latchup from other causes experimentally, a new combination of multiple techniques have been developed and demonstrated. Power supply circumvention, hot-spot monitoring using an infrared camera, and supply current monitoring techniques were implemented for the conformation of the Latchup.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1553-1555
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• 1996

This paper deals with latchup effect in CMOS retrograde well, focusing on their dependence on I/I energy conditions, so we derived some latchup characteristics from simulation for different I/I conditions on implantation energies which were used in process simulation. From these results, we could understand the dependency of CMOS retrograde well latchup on I/I energy condition.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1185-1186
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• 2008

A nuclear explosion emits a transient radiation pulse like gamma rays. Gamma rays have a high energy and cause unexpected effects in semiconductor devices. These effects are mainly referred to dose-rate latcup and dose-rate upset. By transient radiation pulse in CMOS devices, dose-rate latchup is simulated in this paper.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1372-1373
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latchup problem during normal operation. However, a modified NSCR_PPS device with proper junction/channel engineering demonstrates highly latchup immune current- voltage characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.106-113
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• 2000

This study describes how a properly calibrated simulation method could be used to investigate the latchup immunity characteristics among the various high energy ion implanted CMOS twin well (retro-grade/BILLI/BL) structures. To obtain the accurate quantitative simulation analysis of retrograde well, a global tuning procedure and a set of grid specifications for simulation accuracy and computational efficiency are carried out. The latchup characteristics of BILLI and BL structures are well predicted by applying a calibrated simulation method for retrograde well. By exploring the potential contour, current flow lines, and electron/hole current densities at the holding condition, we have observed that the holding voltage of BL structure is more sensitive to the well design rule (p+to well edge space /n +to well edge space) than to the retrograde well itself.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.227-231
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• 2008

A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a $0.35{\mu}m$ 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.32-37
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• 1993

A novel insulated gate bipolar transister (IGBT), called insulated trench cathode IGBT (ISTC-IGBT), is proposed. ISTC-IGBT has a trenched well with the shallow P$^{+}$ juction in the conventional IGBT structure. The proposed structure has the capability of effectively suppressing the parasitic thyristor latchup. The holding current of ISTC-IGBT is about 2.2 times greater than that of the conventional IGBT. Detailed analysis of the latchup characteristics of ISTC-IGBT is performed by using the two-dimensional device simulator, PISCES-II B.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1370-1371
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latchup problem during normal operation. However, a modified NEDSCR device with proper junction / channel engineering demonstrates itself with both the excellent ESD protection performance and the high latchup immunity.

• Journal of Satellite, Information and Communications
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• v.7 no.2
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• pp.18-24
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• 2012

High current behaviors of the extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOSFET) for electrostatic discharge (ESD) protection of high voltage operating LDI (LCD Driver IC) chip are analyzed. Both the transmission line pulse (TLP) data and the thermal incorporated 2-dimensional simulation analysis demonstrate a characteristic double snapback phenomenon after triggering of biploar junction transistor (BJT) operation. Also, background doping concentration (BDC) is proven to be a critical factor to affect the high current behavior of the EDNMOS devices. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.